DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 01/17/2025 and 01/23/2025.
The Examiner acknowledges the Preliminary Amendments filed 01/23/2025.
Claims 1-20 are cancelled.
Claims 21-40 are newly added.
Claims 21-40 are pending.
Claims 21-40 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the objections and rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claim as a continuation of US Application 18/410,175 filed 01/11/2024, now US Patent No. 12,346,603, which claims priority to US Application 16/928,564 filed 07/14/2020, now US Patent No. 11,907,572, which claims priority to provisionally filed Application 62/954,869 filed 12/30/2019 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 01/17/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 01/17/2025 are acceptable for examination purposes.
Claim Objections
Claim 40 is objected to because of the following informalities:
Claim 40 contains a typographical error in the preamble “The metho of claim 33” which appears to be intended to recite “The method of claim 33”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 25 recites “the write data in the read buffer without a transfer of data from a memory device to the read buffer.” Herein the “memory device” lacks proper antecedent basis with respect to the recitation of “a memory device” in claim 21, from which claim 25 depends.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21 and 26-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,346,603, hereinafter referred to as “Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrow scope. Claims 22-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8-9 of the US Patent in view of Mathews et al. (US 10,545,701). In view of Mathews, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate a new entry in a read buffer for transmitted data from the write buffer after determining a read-after-write dependency exists and data is accessible in the write buffer.
Instant Application
US Patent 12,346,603
A memory sub-system comprising: a memory device; and an interface of the memory sub-system comprising a comparator, wherein the interface is coupled to a cache controller; wherein the comparator is configured to: determine whether a read-after-write dependence exists; responsive to determining that the read-after-write dependence exists, identify a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; access write data from a write buffer of the interface utilizing the write ID; store the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and provide the read data to a host from the read buffer of the interface.
A memory sub-system comprising: a memory device; a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device; and an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to: receive a write command addressed to a first address, a read command addressed to a second address from a host, and data corresponding to the write command from the host; responsive to determining that the first address matches the second address and that the write command was inserted into a command buffer of the interface prior to inserting the read command into the command buffer: drop the read command and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry; and provide the data to the host from a read buffer of the interface.
The memory sub-system of claim 21, wherein the comparator is further configured to create a new entry in the read buffer.
The memory sub-system of claim 1, wherein the interface is further configured to, responsive to determining that the first address does not match the second address, provide the read command and the second address to the processing device.
The memory sub-system of claim 22, wherein the comparator is configured to create the new entry in the read buffer utilizing the read ID and the write data as the read data.
The memory sub-system of claim 1, wherein the interface is further to, responsive to determining that the first address matches the second address, provide the data to the host without providing the read command and the second address to the processing device.
The memory sub-system of claim 23, wherein the comparator is configured to store the write data to the read buffer without a transfer of data from a cache memory managed by the cache controller.
The memory sub-system of claim 3, wherein the interface is further configured to: responsive to determining that the first address matches the second address, drop the read command and the second address from the command buffer prior to providing commands in the command buffer to the processing device.
The memory sub-system of claim 23, wherein the comparator is configured to store the write data in the read buffer without a transfer of data from a memory device to the read buffer.
The memory system of claim 4, wherein the interface is further configured to provide the data from a write buffer to the read buffer to provide the data to the host.
The memory sub-system of claim 21, wherein the comparator is configured to determine whether the read-after-write dependence exists by determining whether the write command and a read command are addressed to a same address.
The memory sub-system of claim 4, wherein the interface is further configured to provide the data from the read buffer to input/output lines to provide the data to the host.
A memory sub-system comprising: a memory device; a cache controller; and an interface of the memory sub-system comprising: a comparator; and error memory; wherein the interface is coupled to the cache controller; wherein the comparator is configured to: determine whether a read-after-write dependence exists utilizing the error memory of the interface; responsive to determining that the read-after-write dependence exists, identify a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; access write data from a write buffer of the interface utilizing the write ID; store the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and provide the read data to a host from the read buffer of the interface.
The memory sub-system of claim 4, wherein the interface is further configured to provide the data from the write buffer via the read buffer to input/output lines to provide the data to the host.
The apparatus of claim 27, wherein the comparator is further configured to mark a read command that reads from a same address as the write command in the error memory of the interface.
A method comprising: receiving, at an interface of a memory sub-system and from a host, a write command addressed to a first address and a read command addressed to a second address; storing the write command and the read command in a command buffer of the interface; determining, using a comparator of the interface, whether the first address matches the second address; determining whether data stored in a write buffer of the interface and corresponding to the write command is corrupt; responsive to determining that the first address matches the second address, and that the data is not corrupt: dropping, at the interface, the read command and the second address from the command buffer by sending a signal from the comparator to error correction circuitry of the interface to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry; and providing the data to the host from a read buffer of the interface; and responsive to determining that the first address does not match the second address or that the data is corrupt, providing the read command and the second address to a processing device coupled to a memory device of the memory sub-system and configured to control cache memory for the memory device to store data prior to storing the data on the memory device.
The apparatus of claim 28, wherein the comparator is further configured to identify the write ID and the read ID corresponding to the write command and the read commands that are addressed to a same address.
The method of claim 8, further comprising identifying a write ID of the write command addressed to the first address and a read ID of the read command addressed to the second address responsive to determining that the first address matches the second address.
The apparatus of claim 27, wherein the comparator is further configured to modify an entry of the error memory utilizing the write ID.
The method of claim 9, further comprising storing the data in the read buffer and associating the data in the read buffer with the read ID.
The apparatus of claim 30, wherein the comparator is further configured to update a read-after-write result stored in the error memory utilizing the write ID.
The method of claim 8, further comprising responsive to determining that the first address does not match the second address and that the data is not corrupt, providing the write command and the first address to the processing device.
The apparatus of claim 31, wherein the error memory is configured to simultaneously provide information regarding a result of an error correction code (ECC) and information regarding which commands write and read data from a same address.
The method of claim 8, further comprising responsive to determining that the first address does match the second address and that the data is not corrupt, providing the read command and the read address to the processing device.
A method comprising: determining, by a comparator of an interface of a memory sub-system, whether a read- after-write dependence exists utilizing an error correction code (ECC) of the interface; responsive to determining that the read-after-write dependence exists, identifying, by the comparator, a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; accessing, by the comparator, write data from a write buffer of the interface utilizing the write ID; storing, by the comparator, the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and providing the read data to a host from the read buffer of the interface.
The method of claim 8, further comprising responsive to determining that the data is corrupt, providing the write command and the first address to the processing device to be dropped by the processing device.
The method of claim 33, further comprising storing the write data in the read buffer and associating the write data in the read buffer with the read ID.
The method of claim 8, further comprising determining whether the data corresponding to the write command is corrupt utilizing the error correction circuitry.
The method of claim 33, further comprising identifying the write ID of the write command addressed to a first address and the read ID of a read command addressed to a second address responsive to determining that the first address matches the second address.
The method of claim 14, further comprising: receiving a different write command having a different write ID than a write ID corresponding to the write command; determining that the write command was received prior to the different write command; and storing the determination of whether the first address matches the second address in the error correction circuitry utilizing the different write ID.
The method of claim 35, further comprising responsive to determining that the first address does not match the second address, providing the write command and the first address to a cache controller of the memory sub-system.
The method of claim 15, further comprising: determining whether the write command was received prior to the different write command; providing different data to the host utilizing a read ID responsive to determining that the different write command was received after the write command; and wherein providing the data to the host further comprises providing the data to the host responsive to determining that the different write command was received prior to the write command.
The method of claim 35, further comprising responsive to determining that the first address does match the second address and that the write data is not corrupt, providing the read command and the read address to a cache controller of the memory sub-system.
A memory sub-system, comprising: a memory device; a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device; and an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to: receive a write command addressed to a first address, a first read command and a second read command addressed to a second address from a host, and data corresponding to the write command from the host; responsive to determining that the first address matches the second address and that the data is not corrupt: drop the first read command, the second read command, and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the first read command and the second read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the first read command and the second read command responsive to the first read command and the second read command being marked by the error correction circuitry; and provide the data to the host from a read buffer of the interface; and responsive to determining that the first address does not match the second address or that the data is corrupt, provide the first read command, the second read command, and the second address to the processing device for processing.
The method of claim 34, further comprising responsive to determining that the write data is corrupt, providing the write command and the first address to the cache controller to be dropped by the cache controller.
The memory sub-system of claim 17, wherein the interface is further configured to: store a first determination that the data is not corrupt in the error correction circuitry utilizing a write ID of the write command; store a second determination that the first address matches the second address in the error correction circuitry utilizing the write ID; and refrain from releasing the write ID until the data has been stored to the read buffer utilizing a first read ID and a second read ID corresponding to the first read command and the second read command, respectively.
The method of claim 38, further comprising determining whether the write data corresponding to the write command is corrupt utilizing the ECC.
The memory sub-system of claim 18, wherein the interface is further configured to refrain from releasing the write ID until the data has been stored to the read buffer responsive to the second determination regardless of whether the write command has been provided to the processing device or not.
The metho of claim 33, further comprising preventing a release of the write ID associated with the read-after-write dependence until the read data is provided to the host.
The memory sub-system of claim 17, wherein the interface is further configured to: store a determination that the data is corrupt in the error correction circuitry utilizing the write ID of the write command; and release the write ID responsive to providing the write command to the processing device regardless of whether the first address matches the second address.
Regarding claim 21, the claim of the instant application is substantially similar to that of Claim 1 and Claims 8 and 9 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application. The method step limitations of claims 8 and 9 would be obvious to one of ordinary skill in the art to be executable in the context of the memory sub-system as presented in claim 1 of the US Patent.
Regarding claim 22 of the instant application, the limitations are substantially identical to claims 1, 8, and 9 of the Patent in view of Mathews. Mathews discloses in Column 12, line 56 – Column 13, line 9 transferring of data between write buffer entries and a read buffer in order to handle read-after-write scenarios without requiring memory access.
Regarding claim 23 of the instant application, the limitations are substantially identical to claims 1, 8, and 9 of the Patent in view of Mathews.
Regarding claim 24 of the instant application, the limitations are substantially identical to claims 1, 8, and 9 of the Patent in view of Mathews. As noted above, Mathews discloses the transfer of data between buffers may not involve accessing memory.
Regarding claim 25 of the instant application, the limitations are substantially identical to claims 1, 8, and 9 of the Patent in view of Mathews. As noted above, Mathews discloses the transfer of data between buffers may not involve accessing memory.
Regarding claim 26 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 27 of the instant application, the limitations are substantially identical to claim 17 and 18 of the Patent for similar reasons as identified for claim 21. The error memory of claim 27 is determined to be incorporated within the error correction circuitry as disclosed in claim 17 of the US Patent.
Regarding claim 28 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 29 of the instant application, the limitations are substantially identical to claim 17 and claim 18 of the Patent.
Regarding claim 30 of the instant application, the limitations are substantially identical to claim 17 and claim 18 of the Patent. It would be obvious to one of ordinary skill in the art that the storing of a first determination as performed in claim 18 of the US Patent may involve modification of an entry using the write ID.
Regarding claim 31 of the instant application, the limitations are substantially identical to claim 17, 18, and 19 of the Patent.
Regarding claim 32 of the instant application, the limitations are substantially identical to claim 17, 18, and 19 of the Patent. The US Patent recites steps for marking data and storing data as part of the same step of determining that addresses match.
Regarding claim 33 of the instant application, the limitations are substantially identical to claim 8 and claim 9 of the Patent for similar reasons as identified for claim 21.
Regarding claim 34 of the instant application, the limitations are substantially identical to claim 8, 9, and 10 of the Patent.
Regarding claim 35 of the instant application, the limitations are substantially identical to claim 8 and claim 9 of the Patent.
Regarding claim 36 of the instant application, the limitations are substantially identical to claim 8 and claim 11 of the Patent.
Regarding claim 37 of the instant application, the limitations are substantially identical to claim 8 and claim 12 of the Patent.
Regarding claim 38 of the instant application, the limitations are substantially identical to claim 8 and claim 13 of the Patent.
Regarding claim 39 of the instant application, the limitations are substantially identical to claim 8 and claim 14 of the Patent.
Regarding claim 40 of the instant application, the limitations are substantially identical to claim 17, 18 and 19 of the Patent.
This is a nonstatutory double patenting rejection.
The Examiner notes MPEP Section 804.02 (IV) cited below:
If multiple conflicting patents and/or pending applications are applied in nonstatutory double patenting rejections made in a single application, then prior to issuance of that application, it is necessary to disclaim the terminal part of any patent granted on the application which would extend beyond the expiration date of each one of the conflicting patents and/or applications. A terminal disclaimer fee is required for each terminal disclaimer filed. To avoid paying multiple terminal disclaimer fees, a single terminal disclaimer based on common ownership may be filed, for example, in which the term disclaimed is based on all the conflicting, commonly owned nonstatutory double patenting references. Similarly, a single terminal disclaimer based on a joint research agreement may be filed, in which the term disclaimed is based on all the conflicting nonstatutory double patenting references.
Each one of the commonly owned conflicting nonstatutory double patenting references must be included in the terminal disclaimer to avoid the problem of dual ownership of patents to patentably indistinct inventions in the event that the patent issuing from the application being examined ceases to be commonly owned with any one of the double patenting references that have issued or may issue as a patent. Note that 37 CFR 1.321(c)(3) requires that a terminal disclaimer for commonly owned conflicting claims "[i]nclude a provision that any patent granted on that application or any patent subject to the reexamination proceeding shall be enforceable only for and during such period that said patent is commonly owned with the application or patent which formed the basis for the judicially created double patenting."
Filing a terminal disclaimer including each one of the conflicting nonstatutory double patenting references is also necessary to avoid the problem of separate enforcement of patents to patentably indistinct inventions by parties to a joint research agreement. 37 CFR 1.321(d) sets forth the requirements for a terminal disclaimer where the claimed invention resulted from activities undertaken within the scope of a joint research agreement.
Claims 21 and 26-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11,907,572, hereinafter referred to as “Patent II”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are a broader recitation of those in the US Patent II as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent II may anticipate the claims of the instant application as they are of narrow scope. Claims 22-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of the US Patent II in view of Mathews et al. (US 10,545,701). In view of Mathews, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allocate a new entry in a read buffer for transmitted data from the write buffer after determining a read-after-write dependency exists and data is accessible in the write buffer.
Instant Application
US Patent 11,907,572
A memory sub-system comprising: a memory device; and an interface of the memory sub-system comprising a comparator, wherein the interface is coupled to a cache controller; wherein the comparator is configured to: determine whether a read-after-write dependence exists; responsive to determining that the read-after-write dependence exists, identify a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; access write data from a write buffer of the interface utilizing the write ID; store the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and provide the read data to a host from the read buffer of the interface.
A memory sub-system comprising: a memory device; a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device; and an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to: receive a write command addressed to a first address and a read command addressed to a second address from a host; receive data corresponding to the write command from the host; store the write command and the read command in a command buffer of the interface; store the data in a write buffer of the interface; determine, using the comparator of the interface, whether the first address matches the second address while the write command and the read command are stored in the command buffer; determine, using the comparator of the interface, whether the write command was inserted into the command buffer prior to insertion of the read command into the command buffer by comparing a first identifier (ID) of the write command and a second ID of the read command, wherein the first ID and the second ID are assigned sequentially based on an order in which commands are received from the host; and responsive to determining that the first address matches the second address and that the write command was inserted into the command buffer prior to inserting the read command into the command buffer: drop the read command and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry; forward the data from the write buffer directly to a read buffer of the interface via lines that couple the write buffer to the read buffer; and provide the data to the host from the read buffer; and responsive to determining that the first address does not match the second address, provide the read command and the second address to the processing device.
The memory sub-system of claim 21, wherein the comparator is further configured to create a new entry in the read buffer.
The memory sub-system of claim 1, wherein the interface is further to, responsive to determining that the first address matches the second address, provide the data to the host without providing the read command and the second address to the processing device.
The memory sub-system of claim 22, wherein the comparator is configured to create the new entry in the read buffer utilizing the read ID and the write data as the read data.
The memory sub-system of claim 2, wherein the interface is further configured to: responsive to determining that the first address matches the second address, drop the read command and the second address from the command buffer prior to providing commands in the command buffer to the processing device.
The memory sub-system of claim 23, wherein the comparator is configured to store the write data to the read buffer without a transfer of data from a cache memory managed by the cache controller.
The memory sub-system of claim 3, wherein the interface is further configured to provide the data from the read buffer to input/output lines to provide the data to the host.
The memory sub-system of claim 23, wherein the comparator is configured to store the write data in the read buffer without a transfer of data from a memory device to the read buffer.
A method comprising: receiving, at an interface of a memory sub-system and from a host, a write command addressed to a first address and a read command addressed to a second address; storing the write command and the read command in a command buffer of the interface; determining, using a comparator of the interface, whether the first address matches the second address while the write command and the read command are stored in the command buffer; determining, using the comparator of the interface, whether the write command was inserted into the command buffer prior to insertion of the read command into the command buffer by comparing a write identifier (ID) of the write command and a read ID of the read command, wherein the write ID and the read ID are assigned sequentially based on an order in which commands are received from the host; determining whether data stored in a write buffer of the interface and corresponding to the write command is corrupt; responsive to determining that the first address matches the second address, that the data is not corrupt, and that the write command was inserted into the command buffer prior to inserting the read command into the command buffer: dropping, at the interface, the read command and the second address from the command buffer by sending a signal from the comparator to error correction circuitry of the interface to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry; forwarding the data from the write buffer directly to a read buffer of the interface via lines that couple the write buffer to the read buffer; and providing the data to the host from the read buffer; and responsive to determining that the first address does not match the second address or that the data is corrupt, providing the read command and the second address to a processing device coupled to a memory device of the memory sub-system and configured to control cache memory for the memory device to store data prior to storing the data on the memory device.
The memory sub-system of claim 21, wherein the comparator is configured to determine whether the read-after-write dependence exists by determining whether the write command and a read command are addressed to a same address.
The method of claim 5, further comprising identifying the write ID of the write command addressed to the first address and the read ID of the read command addressed to the second address responsive to determining that the first address matches the second address.
A memory sub-system comprising: a memory device; a cache controller; and an interface of the memory sub-system comprising: a comparator; and error memory; wherein the interface is coupled to the cache controller; wherein the comparator is configured to: determine whether a read-after-write dependence exists utilizing the error memory of the interface; responsive to determining that the read-after-write dependence exists, identify a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; access write data from a write buffer of the interface utilizing the write ID; store the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and provide the read data to a host from the read buffer of the interface.
The method of claim 6, further comprising storing the data in the read buffer and associating the data in the read buffer with the read ID.
The apparatus of claim 27, wherein the comparator is further configured to mark a read command that reads from a same address as the write command in the error memory of the interface.
The method of claim 5, further comprising responsive to determining that the first address does not match the second address and that the data is not corrupt, providing the write command and the first address to the processing device.
The apparatus of claim 28, wherein the comparator is further configured to identify the write ID and the read ID corresponding to the write command and the read commands that are addressed to a same address.
The method of claim 5, further comprising responsive to determining that the first address does match the second address and that the data is not corrupt, providing the read command and the read address to the processing device.
The apparatus of claim 27, wherein the comparator is further configured to modify an entry of the error memory utilizing the write ID.
The method of claim 5, further comprising responsive to determining that the data is corrupt, providing the write command and the first address to the processing device to be dropped by the processing device.
The apparatus of claim 30, wherein the comparator is further configured to update a read-after-write result stored in the error memory utilizing the write ID.
The method of claim 5, further comprising determining whether the data corresponding to the write command is corrupt utilizing the error correction circuitry.
The apparatus of claim 31, wherein the error memory is configured to simultaneously provide information regarding a result of an error correction code (ECC) and information regarding which commands write and read data from a same address.
The method of claim 11, further comprising: receiving a different write command having a different write ID than a write ID corresponding to the write command; determining that the write command was received prior to the different write command; and storing the determination of whether the first address matches the second address in the error correction circuitry utilizing the different write ID.
A method comprising: determining, by a comparator of an interface of a memory sub-system, whether a read- after-write dependence exists utilizing an error correction code (ECC) of the interface; responsive to determining that the read-after-write dependence exists, identifying, by the comparator, a write identifier (ID) and a read ID associated with the read-after-write dependence, wherein the write ID corresponds to a write command having an address to the memory device; accessing, by the comparator, write data from a write buffer of the interface utilizing the write ID; storing, by the comparator, the write data having the write ID as read data to a read buffer of the interface utilizing the read ID; and providing the read data to a host from the read buffer of the interface.
The method of claim 12, further comprising: determining whether the write command was received prior to the different write command; providing different data to the host utilizing the read ID responsive to determining that the different write command was received after the write command; and wherein providing the data to the host further comprises providing the data to the host responsive to determining that the different write command was received prior to the write command.
The method of claim 33, further comprising storing the write data in the read buffer and associating the write data in the read buffer with the read ID.
A memory sub-system, comprising: a memory device; a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device; an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to: receive a write command addressed to a first address and a first read command and a second read command addressed to a second address from a host; receive data corresponding to the write command from the host; store the write command, the first read command, and the second read command in a command buffer of the interface; store the data in a write buffer of the interface; determine, using the comparator of the interface, whether the write command was inserted into the command buffer prior to insertion of the first read command and the second read command into the command buffer by comparing a write identifier (ID) of the write command, a first read ID of the first read command, and a second read ID of the second read command, wherein the write ID, the first read ID, and the second read ID are assigned sequentially based on an order in which commands are received from the host; responsive to determining that the first address matches the second address and that the write command was inserted into the command buffer prior to inserting the read command into the command buffer using the comparator of the interface while the write command, the first read command, and the second read command are stored in the command buffer and that the data is not corrupt: drop the first read command, the second read command, and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the first read command and the second read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the first read command and the second read command responsive to the first read command and the second read command being marked by the error correction circuitry; forward the data from the write buffer directly to a read buffer of the interface via lines that couple the write buffer to the read buffer; and provide the data to the host from the read buffer; and responsive to determining that the first address does not match the second address or that the data is corrupt while the write command, the first read command, and the second read command are stored in the command buffer, provide the first read command, the second read command, and the second address to the processing device for processing.
The method of claim 33, further comprising identifying the write ID of the write command addressed to a first address and the read ID of a read command addressed to a second address responsive to determining that the first address matches the second address.
The memory sub-system of claim 14, wherein the interface is further configured to: store a first determination that the data is not corrupt in the error correction circuitry utilizing the write ID of the write command; store a second determination that the first address matches the second address in the error correction circuitry utilizing the write ID; and refrain from releasing the write ID until the data has been stored to the read buffer utilizing the first read ID and the second read ID corresponding to the first read command and the second read command, respectively.
The method of claim 35, further comprising responsive to determining that the first address does not match the second address, providing the write command and the first address to a cache controller of the memory sub-system.
The memory sub-system of claim 15, wherein the interface is further configured to refrain from releasing the write ID until the data has been stored to the read buffer responsive to the second determination regardless of whether the write command has been provided to the processing device or not.
The method of claim 35, further comprising responsive to determining that the first address does match the second address and that the write data is not corrupt, providing the read command and the read address to a cache controller of the memory sub-system.
The memory sub-system of claim 14, wherein the interface is further configured to: store a determination that the data is corrupt in the error correction circuitry utilizing the write ID of the write command; and release the write ID responsive to providing the write command to the processing device regardless of whether the first address matches the second address.
The method of claim 34, further comprising responsive to determining that the write data is corrupt, providing the write command and the first address to the cache controller to be dropped by the cache controller.
The method of claim 38, further comprising determining whether the write data corresponding to the write command is corrupt utilizing the ECC.
The metho of claim 33, further comprising preventing a release of the write ID associated with the read-after-write dependence until the read data is provided to the host.
Regarding claim 21, the claim of the instant application is substantially similar to that of Claim 1 of the Patent II as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent II notes the differences and the US Patent II thereby presenting a narrower scope establishes that the US Patent II would otherwise anticipate the limitations of the instant application. The method step limitations of claims 8 and 9 would be obvious to one of ordinary skill in the art to be executable in the context of the memory sub-system as presented in claim 1 of the US Patent.
Regarding claim 22 of the instant application, the limitations are substantially identical to claim 1 of the Patent II in view of Mathews. Mathews discloses in Column 12, line 56 – Column 13, line 9 transferring of data between write buffer entries and a read buffer in order to handle read-after-write scenarios without requiring memory access.
Regarding claim 23 of the instant application, the limitations are substantially identical to claim 1 of the Patent II in view of Mathews.
Regarding claim 24 of the instant application, the limitations are substantially identical to claim 1 of the Patent II in view of Mathews. As noted above, Mathews discloses the transfer of data between buffers may not involve accessing memory.
Regarding claim 25 of the instant application, the limitations are substantially identical to claim 1 of the Patent II in view of Mathews. As noted above, Mathews discloses the transfer of data between buffers may not involve accessing memory.
Regarding claim 26 of the instant application, the limitations are substantially identical to claim 1 of the Patent II.
Regarding claim 27 of the instant application, the limitations are substantially identical to claim 14 of the Patent II for similar reasons as identified for claim 21. The error memory of claim 27 is determined to be incorporated within the error correction circuitry as disclosed in claim 14 of the US Patent II.
Regarding claim 28 of the instant application, the limitations are substantially identical to claim 14 of the Patent II.
Regarding claim 29 of the instant application, the limitations are substantially identical to claim 14 of the Patent II.
Regarding claim 30 of the instant application, the limitations are substantially identical to claim 14 of the Patent II. It would be obvious to one of ordinary skill in the art that the storing of a first determination as performed in claim 14 of the US Patent II may involve modification of an entry using the write ID.
Regarding claim 31 of the instant application, the limitations are substantially identical to claim 14 and 15 of the Patent II.
Regarding claim 32 of the instant application, the limitations are substantially identical to claim 14 and 15 of the Patent II. The US Patent II recites steps for marking data and storing data as part of the same step of determining that addresses match.
Regarding claim 33 of the instant application, the limitations are substantially identical to claim 5 of the Patent II for similar reasons as identified for claim 21.
Regarding claim 34 of the instant application, the limitations are substantially identical to claim 5 of the Patent II.
Regarding claim 35 of the instant application, the limitations are substantially identical to claim 5 and claim 6 of the Patent II.
Regarding claim 36 of the instant application, the limitations are substantially identical to claim 5 and claim 8 of the Patent II.
Regarding claim 37 of the instant application, the limitations are substantially identical to claim 5 and claim 9 of the Patent II.
Regarding claim 38 of the instant application, the limitations are substantially identical to claim 8, 11, and 12 of the Patent II.
Regarding claim 39 of the instant application, the limitations are substantially identical to claim 8, 11, and 12 of the Patent II.
This is a nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mathews et al. (US 10,545,701) – Columns 12-13 wherein addressing RAW hazards is discussed.
Stevens (US 8,762,682) wherein configurable datapaths trough a command interface is provided to service read commands targeting the same address as a prior write command.
Tsukishiro (US 2010/0211746) wherein transfer from cache to write buffers and read buffers based on target addresses is discussed.
Shelor (US 2008/0126642) wherein directional buffers are discussed.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135