DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims, specification, and remarks filed on 4/10/2025,
IDS filed on 12/17/2025, 8/19/2025, and 4/10/2025.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 3/25/2021.
Drawings
The Examiner contends that the drawings submitted on 1/17/2025 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,242,846. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent No. 12,242,846 contains every element of claims 1-20 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
Patent 12,242,846
1. An apparatus comprising:
1. An apparatus comprising:
an integrated circuit chip, comprising:
an integrated circuit chip, comprising:
a plurality of registers to store a plurality of data elements, including 8-bit floating point data elements and 32-bit floating point data elements;
decode circuitry to decode a single matrix instruction having fields to indicate an opcode and locations of a first source matrix including a first plurality of 8-bit floating point data elements encoded in a first 8-bit floating point format, a second source matrix including a second plurality of the 8-bit floating point data elements encoded in a second 8-bit floating point format, and a third source matrix including a plurality of 32- bit floating point data elements,
decode circuitry to decode a single matrix instruction having fields to indicate an opcode and locations of a first source matrix including a first plurality of the 8-bit floating point data elements encoded in a first 8-bit floating point format, a second source matrix including a second plurality of the 8-bit floating point data elements encoded in a second 8-bit floating point format, and a third source matrix including a plurality of 32- bit floating point data elements,
wherein the first 8-bit floating point format comprises a sign bit, a 5-bit exponent value, and a 2-bit mantissa value and the second 8-bit floating point format comprises a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and
wherein the first 8-bit floating point format comprises a sign bit, a 5-bit exponent value, and a 2-bit mantissa value and the second 8-bit floating point format comprises a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and
execution circuitry including matrix processing circuitry, wherein responsive to the single matrix instruction, the execution circuitry is to generate a plurality of products based on the first plurality of 8-bit floating point data elements and the second plurality of 8-bit floating point data elements, and accumulate each product of the plurality of products with a corresponding 32-bit floating point data element of the third source matrix to generate a corresponding 32-bit floating point result data element of a result matrix.
execution circuitry including matrix processing circuitry to accelerate matrix operations, wherein responsive to the single matrix instruction, the execution circuitry is to generate a plurality of products based on the first plurality of the 8-bit floating point data elements and the second plurality of the 8-bit floating point data elements, and accumulate each product of the plurality of products with a corresponding 32-bit floating point data element of the third source matrix to generate a corresponding 32-bit floating point result data element of a result matrix.
Independent claims 13 and 17 are read upon by independent claims 13 and 17 of U.S. Patent No. 12,242,846 and are rejected for the same reasons. Dependent claims 2-12, 14-16, and 18-20 are read upon by the dependent claims 2-12, 14-16, and 18-20 of U.S. Patent No. 12,242,846.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Whatmough et al. (U.S. 2019/0311243), taught a systolic convolution neural network.
Lyuh et al. (U.S. 2019/0079801), taught neural network PE array.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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