Detail Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 01-17-2025 under new application being continuation of parent application # 17/332,596 filed on 05/27/2021; matured to patent # 12236498; which have been placed of record in the file. Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04-07-2025, 09-08-2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Doyle Peter L (Us 20180286110 A1) hereinafter referenced as Doyle in view of Schneider Bengt-Olaf et al. (US 9002125 B2) hereinafter referenced as Schneider et al. and Seiler Larry (US 20170345207 A1) hereinafter referenced as Seiler.
Regarding Claim 1, Doyle discloses a processor (fig. 1, item 02, para. 29) comprising: a rasterizer ( fig. 2, Item 226, para. 49) to generate a fragment of pixel data (para. 122) including a plurality of blocks of pixel data (para. 235), each block including multiple pixels (para. 235); a depth pipeline to receive the fragment (para. 122), the depth pipeline including at least first depth test hardware (paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye) and second depth test hardware ((paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye), the first depth test hardware to perform a coarse depth test including determining a minimum depth and a maximum depth for each block (please see paras. 53, 122-123); and a depth buffer to store depth data (para. 49); wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (para. 122).
However, Doyle fails to disclose passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
However, prior art of Schneider et al. disclose processor (abstract), rasterizer generate fragment of pixel data (col. 1, Lines 32-56), a depth pipeline to receive the fragment (see Ibid., Col.1. Line 52 to Col. 2, Line 2 discloses a depth pipeline to receive the fragment), the depth pipeline including at least first depth test hardware (see implicit rendering; col. 2 Lines 22-34, comparison to existing depths) and second depth test hardware (see implicit rendering; col. 2 Lines 22-34, other comparisons further), first depth test hardware passes first depth test requirements ( implicit rendering; col. 2 Lines 22-34) passes (Col. 9, Lines 3-11, discloses implicitly suggests there is no fragmented bits tested and compressed are left to be stored further disclosing depth test requirements is met and test has passed, compression format depending on the result of the tests. ) and wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (Fig. 9, Col. 11, Lines 35-48, fully covering z-plane), to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane (Col. 5, Lines 21-43) and a coarse/first and finer/second depth test (or test units) as such, Schneider et al. does mention the comparison regarding visibility to existing depths in the Z-buffer col. 2, Lines 22-34, Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed). Further Schneider et al. does disclose the separation of tiles into blocks of pixels, as subdivision of the tiles (see e.g. Fig. 20), test for tiles coded using a compressed z-plane, or several compressed planes (Col. 9, Lines 24-57), arithmetic z-compression format: such format is based on the compressed planes, used as prediction, plus the addition of a residual (see col. 6, Line 33-col. 7, Line 4, also discloses the decision regarding the suitability of a tile for such coding, actually, presumes that the residuals are small enough so they are limited to "the mantissa bits), and whether the maximum and minimum depths in the tile have the same sign and exponent (please see Col. Line 39-56).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Schneider et al. teaches passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Schneider et al. performs the same function as it does separately of computer system with a graphics processing unit that stores compressed graphics information in a frame buffer.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane, as disclosed by Schneider et al. thereby able to compressed and store all the Z-data as Schneider et al. discusses at col. 2, lines 58-60.
Further Regarding Claim 1, Doyle fails to disclose z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
However, prior art of Seiler discloses z-plane representations based on block exponents (see para.33) allowing for fixed points mantissas and common exponent (see paras.65-66, 80 disclosing common exponent).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Seiler teaches z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Seiler performs the same function as it does separately of computer graphics technologies to facilitate compact storage of the depth (Z) values at positions within a triangle. More particularly, during an interpolation, encoding, and/or storing processes in a graphic pipeline for rendering the 3D scenes.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include z-plane representations based on block exponents allowing for fixed points mantissas and common exponent, as disclosed by Seiler thereby, If an exponent is needed, e.g. to represent Float32 depth values, the exponent should be identical in each compression block's Z-plane, so that each Zref value has the same absolute precision and provides ways to specify Z-planes for block compression that prevent inter-block artifacts and that support the common depth formats as Seiler discusses at paras. 33, 66..
Regarding Claim 2, Doyle discloses the processor is further to write the compressed depth plane from the depth buffer to a cache (para. 48, discloses buffer data written to cache).
Please also see prior art of Schneider et al. Col. 6 Line 14-32 discloses compressed data processed for depth and store into the buffer.
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 3, Schneider et al. discloses the processor further includes a decompressor, the decompressor to decompress the compressed depth plane from the cache, wherein the decompression of the compressed depth plane (Col. 6, Lines 14-32) includes
Doyle discloses generating depth values using unsigned mathematics operation (para. 216 discloses computing depth values storing in the buffer).
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 4, Schneider et al. discloses the second depth hardware is to perform per pixel depth calculation (see implicit rendering; col. 2 Lines 22-34, comparison to existing depths disclosing first and second depth hardware, Col. 5 Line 64 to Col. 6, Line 25 disclosing computing pixel data second depth hardware, please also see fig.9).
Regarding Claim 5, Schneider et al. discloses upon determining that the fragment does not meet the requirements, the processor is to provide the fragment to the second depth test hardware for per pixel interpolation and to transfer per pixel values to the depth buffer.(Col. 9, Lines 3-11).
Regarding Claim 6, Schneider et al. discloses the compressed depth plane is written to the depth buffer at a rate for the coarse depth test (the comparison regarding visibility to existing depths in the Z-buffer see col. 2, Lines 22-34; Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed).
Regarding Claim 7, Seiler discloses the compressed depth plane includes: a baseline value for each block of the plurality of blocks of the tile; an X offset value and a Y offset value for the tile; and a depth sign and a depth exponent (please see fig. 5, Zref and slopes para. 31, 33, 81, 82, discloses the compressed depth plane includes: a baseline value for each block of the plurality of blocks of the tile; an X offset value and a Y offset value for the tile; and para. 65, 66, 80 a depth sign and a depth exponent).
Regarding Claim 8, Seiler discloses the X offset value and the Y offset value for a block are based at least in part on a slope in an X direction for depth values of the block and a slope in a Y direction for the block (please see fig. 5, Zref and slopes para. the X offset value and the Y offset value for a block are based at least in part on a slope in an X direction for depth values of the block and a slope in a Y direction for the block).
Regarding Claim 9, Seiler discloses the baseline value for a block is a minimum depth of the block (para. 0060 and trivial in view of the use of common sign and unsigned operations).
Regarding Claim 10, Schneider et al. discloses each block is a 4 by 4 block of pixels and wherein the tile is an 8 by 8 tile of pixels (Col. 1, Lines 33-42).
Please also see prior art of Seiler disclosure at paras 42, 59, fig. 3
Regarding Claim 11, Doyle discloses a system comprising: one or more processors including a graphics processor; a memory for storage of data; and a cache memory; wherein the graphics processor includes (fig. 1, para. 29, 30, 45) include a rasterizer (fig. 2, Item 226, para. 49) to generate a fragment of pixel data (para. 122) including a plurality of blocks of pixel data (para. 235), each block including multiple pixels (para. 235); a depth pipeline to receive the fragment (para. 122), the depth pipeline including at least first depth test hardware (paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye) and second depth test hardware ((paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye), the first depth test hardware to perform a coarse depth test including determining a minimum depth and a maximum depth for each block (please see paras. 53, 122-123); and a depth buffer to store depth data (para. 49); wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (para. 122).
However, Doyle fails to disclose passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
However, prior art of Schneider et al. disclose processor (abstract), rasterizer generate fragment of pixel data (col. 1, Lines 32-56), a depth pipeline to receive the fragment (see Ibid., Col.1. Line 52 to Col. 2, Line 2 discloses a depth pipeline to receive the fragment), the depth pipeline including at least first depth test hardware (see implicit rendering; col. 2 Lines 22-34, comparison to existing depths) and second depth test hardware (see implicit rendering; col. 2 Lines 22-34, other comparisons further), first depth test hardware passes first depth test requirements ( implicit rendering; col. 2 Lines 22-34) passes (Col. 9, Lines 3-11, discloses implicitly suggests there is no fragmented bits tested and compressed are left to be stored further disclosing depth test requirements is met and test has passed, compression format depending on the result of the tests. ) and wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (Fig. 9, Col. 11, Lines 35-48, fully covering z-plane), to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane (Col. 5, Lines 21-43) and a coarse/first and finer/second depth test (or test units) as such, Schneider et al. does mention the comparison regarding visibility to existing depths in the Z-buffer col. 2, Lines 22-34, Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed). Further Schneider et al. does disclose the separation of tiles into blocks of pixels, as subdivision of the tiles (see e.g. Fig. 20), test for tiles coded using a compressed z-plane, or several compressed planes (Col. 9, Lines 24-57), arithmetic z-compression format: such format is based on the compressed planes, used as prediction, plus the addition of a residual (see col. 6, Line 33-col. 7, Line 4, also discloses the decision regarding the suitability of a tile for such coding, actually, presumes that the residuals are small enough so they are limited to "the mantissa bits), and whether the maximum and minimum depths in the tile have the same sign and exponent (please see Col. Line 39-56).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Schneider et al. teaches passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Schneider et al. performs the same function as it does separately of computer system with a graphics processing unit that stores compressed graphics information in a frame buffer.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane, as disclosed by Schneider et al. thereby able to compressed and store all the Z-data as Schneider et al. discusses at col. 2, lines 58-60.
Further Regarding Claim 11, Doyle fails to disclose z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
However, prior art of Seiler discloses z-plane representations based on block exponents (see para.33) allowing for fixed points mantissas and common exponent (see paras.65-66, 80 disclosing common exponent).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Seiler teaches z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Seiler performs the same function as it does separately of computer graphics technologies to facilitate compact storage of the depth (Z) values at positions within a triangle. More particularly, during an interpolation, encoding, and/or storing processes in a graphic pipeline for rendering the 3D scenes.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include z-plane representations based on block exponents allowing for fixed points mantissas and common exponent, as disclosed by Seiler thereby, If an exponent is needed, e.g. to represent Float32 depth values, the exponent should be identical in each compression block's Z-plane, so that each Zref value has the same absolute precision and provides ways to specify Z-planes for block compression that prevent inter-block artifacts and that support the common depth formats as Seiler discusses at paras. 33, 66..
Regarding Claim 12, Doyle discloses the processor is further to write the compressed depth plane from the depth buffer to a cache (para. 48, discloses buffer data written to cache).
Please also see prior art of Schneider et al. Col. 6 Line 14-32 discloses compressed data processed for depth and store into the buffer.
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 13, Schneider et al. discloses the processor further includes a decompressor, the decompressor to decompress the compressed depth plane from the cache, wherein the decompression of the compressed depth plane (Col. 6, Lines 14-32) includes
Doyle discloses generating depth values using unsigned mathematics operation (para. 216 discloses computing depth values storing in the buffer).
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 14, Schneider et al. discloses upon determining that the fragment does not meet the requirements, the processor is to provide the fragment to the second depth test hardware for per pixel interpolation and to transfer per pixel values to the depth buffer.(Col. 9, Lines 3-11).
Regarding Claim 15, Schneider et al. discloses the compressed depth plane is written to the depth buffer at a rate for the coarse depth test (the comparison regarding visibility to existing depths in the Z-buffer see col. 2, Lines 22-34; Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed).
Regarding Claim 16, Seiler discloses the compressed depth plane includes: a baseline value for each block of the plurality of blocks of the tile; an X offset value and a Y offset value for the tile; and a depth sign and a depth exponent (please see fig. 5, Zref and slopes para. 31, 33, 81, 82, discloses the compressed depth plane includes: a baseline value for each block of the plurality of blocks of the tile; an X offset value and a Y offset value for the tile; and para. 65, 66, 80 a depth sign and a depth exponent).
Regarding Claim 17, Doyle discloses a processor (fig. 1, item 02, para. 29) comprising: a rasterizer ( fig. 2, Item 226, para. 49) to generate a fragment of pixel data (para. 122) including a plurality of blocks of pixel data (para. 235), each block including multiple pixels (para. 235); a depth pipeline to receive the fragment (para. 122), the depth pipeline including at least first depth test hardware (paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye) and second depth test hardware ((paras. 53, 122-123, 145 discloses graphic processor hardware performs plurality of functions including first depth test for right (or left) eye), the first depth test hardware to perform a coarse depth test including determining a minimum depth and a maximum depth for each block (please see paras. 53, 122-123); and a depth buffer to store depth data (para. 49); wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (para. 122).
However, Doyle fails to disclose passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
However, prior art of Schneider et al. disclose processor (abstract), rasterizer generate fragment of pixel data (col. 1, Lines 32-56), a depth pipeline to receive the fragment (see Ibid., Col.1. Line 52 to Col. 2, Line 2 discloses a depth pipeline to receive the fragment), the depth pipeline including at least first depth test hardware (see implicit rendering; col. 2 Lines 22-34, comparison to existing depths) and second depth test hardware (see implicit rendering; col. 2 Lines 22-34, other comparisons further), first depth test hardware passes first depth test requirements ( implicit rendering; col. 2 Lines 22-34) passes (Col. 9, Lines 3-11, discloses implicitly suggests there is no fragmented bits tested and compressed are left to be stored further disclosing depth test requirements is met and test has passed, compression format depending on the result of the tests. ) and wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data (Fig. 9, Col. 11, Lines 35-48, fully covering z-plane), to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane (Col. 5, Lines 21-43) and a coarse/first and finer/second depth test (or test units) as such, Schneider et al. does mention the comparison regarding visibility to existing depths in the Z-buffer col. 2, Lines 22-34, Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed). Further Schneider et al. does disclose the separation of tiles into blocks of pixels, as subdivision of the tiles (see e.g. Fig. 20), test for tiles coded using a compressed z-plane, or several compressed planes (Col. 9, Lines 24-57), arithmetic z-compression format: such format is based on the compressed planes, used as prediction, plus the addition of a residual (see col. 6, Line 33-col. 7, Line 4, also discloses the decision regarding the suitability of a tile for such coding, actually, presumes that the residuals are small enough so they are limited to "the mantissa bits), and whether the maximum and minimum depths in the tile have the same sign and exponent (please see Col. Line 39-56).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Schneider et al. teaches passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Schneider et al. performs the same function as it does separately of computer system with a graphics processing unit that stores compressed graphics information in a frame buffer.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane, as disclosed by Schneider et al. thereby able to compressed and store all the Z-data as Schneider et al. discusses at col. 2, lines 58-60.
Further Regarding Claim 17, Doyle fails to disclose z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
However, prior art of Seiler discloses z-plane representations based on block exponents (see para.33) allowing for fixed points mantissas and common exponent (see paras.65-66, 80 disclosing common exponent).
Doyle teaches technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader.
Doyle teaches the rasterization unit is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The rasterizer then outputs processed graphics data that is stored in graphics memory. In some embodiments the rasterization unit includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by the rasterization unit can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.
Seiler teaches z-plane representations based on block exponents allowing for fixed points mantissas and common exponent.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Doyle performs the same function as it does separately of optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry.
Seiler performs the same function as it does separately of computer graphics technologies to facilitate compact storage of the depth (Z) values at positions within a triangle. More particularly, during an interpolation, encoding, and/or storing processes in a graphic pipeline for rendering the 3D scenes.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify the invention of Doyle to include z-plane representations based on block exponents allowing for fixed points mantissas and common exponent, as disclosed by Seiler thereby, If an exponent is needed, e.g. to represent Float32 depth values, the exponent should be identical in each compression block's Z-plane, so that each Zref value has the same absolute precision and provides ways to specify Z-planes for block compression that prevent inter-block artifacts and that support the common depth formats as Seiler discusses at paras. 33, 66..
Regarding Claim 18, Doyle discloses the processor is further to write the compressed depth plane from the depth buffer to a cache (para. 48, discloses buffer data written to cache).
Please also see prior art of Schneider et al. Col. 6 Line 14-32 discloses compressed data processed for depth and store into the buffer.
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 19, Schneider et al. discloses the processor further includes a decompressor, the decompressor to decompress the compressed depth plane from the cache, wherein the decompression of the compressed depth plane (Col. 6, Lines 14-32) includes
Doyle discloses generating depth values using unsigned mathematics operation (para. 216 discloses computing depth values storing in the buffer).
Please also see prior art of Seiler please see para. 33, 46, 56, 170.
Regarding Claim 20, Schneider et al. discloses the first depth test is a coarse depth test, and wherein the plurality of depth tests further includes an intermediate depth test to perform per pixel depth calculation (Col. 5, Line 64 to Col. 6, Line13, mention the comparison regarding visibility to existing depths in the Z-buffer col. 2, Lines 22-34, Since such check is performed routinely in the literature in two steps, coarse and fine, the existence of both steps is regarded as implicitly disclosed).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No.12,236,498 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Comparison of Instant application Claims 1-20 to over claims 1-16 of U.S. Patent No. 12,236,498 B2 as follows:
Instant US Application Number
19029189
US Patent Number
US 12,236,498 B2
1. A processor comprising: a rasterizer to generate a fragment of pixel data including a plurality of blocks of pixel data, each block including multiple pixels; a depth pipeline to receive the fragment, the depth pipeline including at least first depth test hardware and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining a minimum depth and a maximum depth for each block; and a depth buffer to store depth data; wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes the first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.
US 12,.236,498 B2
1. A processor comprising: a rasterizer to generate a fragment of pixel data including a plurality of blocks of pixel data, each block including multiple pixels; a depth pipeline to receive the fragment, the depth pipeline including at least first depth test hardware and second depth test hardware, the first depth test hardware to perform a first depth test including determining a minimum depth and a maximum depth for each block and the second depth hardware to perform a second depth test including per pixel interpolation; and a depth buffer to store depth data; wherein the processor is to: determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes the first depth test performed by the first depth test hardware, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, upon determining that the fragment meets the requirements, generate a compressed depth plane utilizing data from the first depth test, and update the depth buffer with the compressed depth plane, and upon determining that the fragment does not meet the requirements, provide the fragment to the second depth test hardware for per pixel interpolation to generate per pixel values, and transfer the generated per pixel values to the depth buffer.
Note the comparison of independent claim 1 of instant application, to claim 1 of U.S. Patent No. 12,236,498 B2 to avoid 101 statutory double patenting rejections the claims limitation by curtailing the details and language has been changed. However, instant application independent claim limitations are described in independent claims of the parent applications. They both are merely claiming same “Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.”.
Claims 1-3, 6-13 and 15-19 of the instant application are same or similar to Claims 1-16 of the Patent No. 12,236,498 B2, however, instant application claims are not in same order as parent patented application, Patent No. 12,236,498 B2, however, the instant application 16 claims do map to 16 claims of the parent patented application, Patent No. 12,236,498 B2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant is requested review cited prior art cited on USPTO 892.
The prior art of Hasselgren Jon N et al. (US 20150269771 A1) disclosure; paras. 28-60, disclosing a depth buffer architecture includes a rasterizer to identify which pixels lie within the triangle currently being rendered. In order to maximize memory coherency for the rest of the architecture, it is often beneficial to first identify which tiles (a collection of W×H pixels) overlap the triangle. When the rasterizer finds a tile that partially overlaps the triangle, it distributes the pixels in that tile over a number of pixel pipelines. The purpose of each pixel pipeline is to compute the depth and color of a pixel. Each pixel pipeline contains a depth test unit, responsible for discarding pixels that are occluded by the previously drawn geometry. The depth unit includes a memory, in one embodiment, that is a random access memory. It also includes a tile table cache temporarily storing the z.sub.max-mask representation for each tile and backed by the memory, a tile cache which is also backed by the memory and temporarily stores per-sample depth values for rapid access, optionally a z.sub.max-feedback computation which updates the z.sub.max representation in the tile table 30 each time a tile is evicted from the tile cache, a compressor, and a decompressor, as well as a coverage mask buffer 34. The tile table cache stores the z.sub.max representation and header information, for example one or more flags indicating which compression algorithm is used to compress a tile of depth values, separately from the depth buffer data. In maximum depth culling, often called hierarchical occlusion culling, the maximum depth, z.sub.max, of a tile is stored and maintained per tile. If the estimated conservative minimum depth of a triangle inside a tile is greater than the tile's z.sub.max, then the triangle is completely occluded inside that tile. In this case, the per-sample depth values do not need to be read from memory, and no further processing is needed within the tile for that triangle. This technique is sometimes called z.sub.max-culling. In addition, one may also store the minimum depth, z.sub.min, of the depths in a tile, and avoid depth reads if a triangle fully covers a tile, and the triangle's estimated conservative maximum depth is smaller than the z.sub.min, in which case the triangle will overwrite all depths in the tile (assuming no alpha/stencil test etc).
The prior art of Farrell Robert L et al. (US 20150178982 A1) disclosure; paras. 26-77, disclosing, One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous. Receiving a source data group of pixels or samples bounded within a rasterizer tile; determining a source depth plane equation representative of the source data group; determining source depth data by evaluating the source depth plane equation at each of four corners of the source data group bound; determining destination depth data for positions in a destination depth plane corresponding to the four corners; comparing the source depth data with the destination depth data; and storing a representation of a prevailing group of pixels or samples identified by the corner depth test, the representation in either a depth plane equation format in response to the depth values being continuous over the source data bound, or a depth minimum/maximum format in response to the depth values being discontinuous over the source data bound. A graphics processor includes a first means for receiving a source data group of pixels or samples bounded within a rasterizer tile. A graphics processor includes a second means coupled to the first means for determining a source depth plane equation representative of the source data group. A graphics processor includes a third means coupled to the second means for determining source depth data by evaluating the source depth plane equation at each of four corners of the source data group bound. A graphics processor includes a fourth means coupled to the third means for determining destination depth data for positions in a destination depth plane corresponding to the four corners. A graphics processor includes a fifth means coupled to the fourth means for performing a corner depth test by comparing the source depth data with the destination depth data.
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Commissioner of Patents and Trademarks
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/Prabodh M Dharia/
Primary Examiner
Art Unit 2629
06-10-2026
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