DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on July 2, 2026 have been fully considered but they are not persuasive.
Applicant’s Argument(s):
Regarding claims 2, 9, and 16, the Applicant argues “Nygren's description of "an electrical interface routing 120 of conductor lines 124-125" (Nygren [0025]) does not disclose "a plurality of channels configured to communicate binary signaling and multi-level signaling," as recited in amended independent claim 2. Nygren states that the data and control channels defined within the interface are "to enable signal information to be exchange by the die." Id. However, Nygren makes no indication that the signal information supports communication of both "binary signaling and multi-level signaling, as recited in amended independent claim 2. Further, Nygren does not disclose "a multi-level signal . .. [that] represents a plurality of bits of information," as recited in amended independent claim 2. In particular, Nygren makes no mention of communicating any multi-level signaling which conveys multiple bits of information. Thus, Nygren does not disclose all the features of amended independent claim 2.”
Examiner’s Response:
Regarding the argument set forth above, Examiner disagrees with the Applicant and submits that, given the claims their broadest reasonable interpretations, Nguyen teaches an interposer coupled with the array of memory cells and the controller (Fig. 1, interposer 120, memory cells 112, 114, and 116), and comprising a plurality of channels (signal channels/lines 124 and/or route channels/lines 125) configured to communicate (exchange signals comprising bits over said channels/lines, wherein exchange means giving something (in this case signal(s)) and receiving something (in this case signal(s)) binary signaling and multi- level signaling, wherein a multi-level signal of the multi-level signaling represents a plurality of bits of information (Nguyen, paragraph [0024] states that signals comprise bits, as a result, Nguyen teaches binary signaling and multi-level signaling that represents multiple bits are exchanged/communicated over said channels between processor die 102 and interposer 120). Emphasis added.
For these reasons, the rejection is maintained and this Office Action is made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 5-6, and 8 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Nygren et al. (hereinafter referred to as “Nygren”, US 2013/0159587).
As to claim 2, Nygren teaches an apparatus (Fig. 1), comprising: an array of memory cells (Fig. 1, memory cells 112, 114, and 116, paragraphs [0025] and [0027]); a controller configured to control operation of the array of memory cells (Fig. 1, GPU/CPU 102, paragraph [0026]); and an interposer coupled with the array of memory cells and the controller (Fig. 1, interposer 120, paragraphs [0025]-[0029]), and comprising a plurality of channels configured to communicate binary signaling and multi- level signaling, wherein a multi-level signal of the multi-level signaling represents a plurality of bits of information (paragraphs [0024] and [0030]), wherein each channel of the plurality of channels of the interposer is independent from other channels of the plurality of channels of the interposer (Fig. 1, interposer 120, channels 124-125, paragraphs [0025]-[0029] and [0039]), and wherein the plurality of channels comprises one or more unidirectional channels and one or more bidirectional channels (paragraph [0023]).
As to claim 5, Nygren further teaches the plurality of channels is configured to connect the array of memory cells with the controller (Fig. 1, GPU/CPU 102, channels124 and 125, paragraphs [0026] and [0030]).
As to claim 6, Nygren further teaches the controller is further configured to: select one or more of the plurality of channels for communicating data with the array of memory cells (paragraph [0030]).
As to claim 8, Nygren further teaches the controller is configured to: select a combination of the one or more unidirectional channels and the one or more bidirectional channels; and communicate a signal to the array of memory cells via the selected combination of the one or more unidirectional channels and the one or more bidirectional channels, wherein the signal comprises a multi-level signal (paragraphs [0023]-[0024] and [0030], wherein paragraph [0023] states “one or more integrated circuit die are provided with multiple data channels that are routed across bidirectional input/output (I/O) interconnect paths, as well as to unidirectional channels (e.g., pinput or output) interconnect paths, including one or more extra or redundant I/O interconnect paths that can be used as replacement I/O interconnect paths if any of the regular channel interconnect paths fail, paragraph [0030] states “the extra or replacement I/O interconnect channels may include one or more redundant channels (e.g., R1, R2) for internal signaling with the stacked memory 110-116. In addition or in the alternative, one or more redundant channels (e.g., R3) may be included for external signaling. In operation, the processor die 102 ordinarily uses regular or mission-mode 110 interconnect channels D0-D7 to exchange signal information with the stacked memory 110-116 over routing lines 125.”, and paragraph [0024] states that the signals are comprised of bits. It is noted that bits are multi-level (i.e., two level) signals.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4, 9-14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nygren in view of Jeong (US 2016/0028407).
As to claim 3, Nygren further teaches a base coupled with the interposer and the array of memory cells, wherein the base comprises input/output circuitry coupled with one or more of the plurality of channels and (Figs. 1-2, logic interface chip 110, R/MUX 202, paragraphs [0027], [0030], and [0035]).
Nygren does not expressly teach the base is configured to buffer data communicated to and from the array of memory cells.
Jeong further teaches a semiconductor apparatus comprising: an array of memory cells (Figs. 1-2, memory 140, memory cells 220) and a base (Fig. 2, base die 210), wherein the base is configured to buffer data communicated to and from the array of memory cells (paragraphs [0027]-[0028]).
It would have been obvious to one of ordinary skill in the art that the base is configured to buffer data communicated to and from the array of memory cells in order to efficiently reduce the package area of the semiconductor apparatus when using the stacked chips configuration.
As to claims 4, 11, and 18, Nygren further teaches that the plurality of bits represented by the multi-level signal received (paragraph [0024]).
Nygren does not expressly teach the base is configured to determine a signal received via the plurality of channels and write the signal to one or more memory cells of the array of memory cells.
Jeong further teaches the base is configured to determine a signal received via the plurality of channels and write the signal to one or more memory cells of the array of memory cells (Figs. 1-2, paragraphs [0027]-[0028] and [0034]).
It would have been obvious to one of ordinary skill in the art that the base is configured to determine the plurality of bits represented by a signal received via the plurality of channels and write the plurality of bits to one or more memory cells of the array of memory cells in order for the apparatus to have its intended use such as reading signals from and writing signals to memory cells.
As to claim 9, Nygren teaches a method, comprising: identifying, by a controller of a memory device data to be communicated/routed to an array of memory cells (Figs. 1-2, CPU/GPU (controller) 102, memory cells 110, 114, and 116, paragraph [0025] and [0027]); and transmitting, by the controller via an interposer coupled with the controller and the array of memory cells, a multi-level signal (i.e., bits, paragraph [0024]) to the array of memory cells, wherein the multi-level signal represents a plurality of bits of information (paragraphs [0024] and [0030]) and is transmitted via one or more channels of a plurality of channels included in the interposer (Figs. 1-2, CPU/GPU 102, channels 124-125, interposer 120, paragraphs [0025]-[0028]), wherein each channel of the plurality of channels is independent from other channels of the plurality of channels of the interposer (paragraph [0039]), and wherein the plurality of channels comprises one or more unidirectional channels and one or more bidirectional channels (Figs. 1-2, channels 124-125, paragraphs [0023] and [0039]).
Nygren does not expressly teach identifying, by a controller of a memory device, data to be written to an array of memory cells.
Jeong further teaches identifying, by a controller of a memory device, data to be written to an array of memory cells (Figs. 1-2, paragraphs [0025], [0027]-[0028], and [0034]).
It would have been obvious to one of ordinary skill in the art to identify, by a controller of a memory device, data to be written to an array of memory cells in order for the apparatus to have its intended use such as reading signals from and writing signals to memory cells.
As to claims 10 and 17, Nygren further teaches transmitting the multi-level signal (or bits) to a base coupled with the interposer and the array of memory cells, wherein the base comprises input/output circuitry coupled with one or more of the plurality of channels; and communicating, by the base, the signal to the array of memory cells (Figs. 1-2, paragraphs [0025]-[0027] and [0029]).
As to claims 12 and 19, Nygren further teaches receiving, via one or more second channels of the plurality of channels, second data from the array of memory cells based at least in part on transmitting the signal (Figs. 1-2, CPU/GPU 102, channels 124-125, interposer 120, paragraphs [0025]-[0028]).
As to claims 13 and 20, Nygren further teaches selecting, by the controller, a combination of the one or more unidirectional channels and the one or more bidirectional channels for communicating the signal, wherein transmitting the signal across the one or more channels is based at least in part on selecting the combination of the one or more unidirectional channels and the one or more bidirectional channels (paragraphs [0023]-[0024] and [0030], wherein paragraph [0023] states “one or more integrated circuit die are provided with multiple data channels that are routed across bidirectional input/output (I/O) interconnect paths, as well as to unidirectional channels (e.g., pinput or output) interconnect paths, including one or more extra or redundant I/O interconnect paths that can be used as replacement I/O interconnect paths if any of the regular channel interconnect paths fail, paragraph [0030] states “the extra or replacement I/O interconnect channels may include one or more redundant channels (e.g., R1, R2) for internal signaling with the stacked memory 110-116. In addition or in the alternative, one or more redundant channels (e.g., R3) may be included for external signaling. In operation, the processor die 102 ordinarily uses regular or mission-mode 110 interconnect channels D0-D7 to exchange signal information with the stacked memory 110-116 over routing lines 125.”, Figs. 1-2, CPU/GPU 102, channels 124-125, interposer 120, paragraphs [0025]-[0028]).
As to claim 14, Nygren further teaches the signal comprises a multi-level signal (paragraph [0030] states that the signals are comprised of bits. It is noted that bits are multi-level (i.e., two level) signals.).
As to claim 16, Nygren teaches a memory device, comprising: an array of memory cells (Figs. 1-2, array of memory cells 112, 114, and 116); an interposer coupled with the array of memory cells and comprising a plurality of channels (Figs. -2, interposer 120, channels 124-125, array of memory cells 112, 114, and 116, paragraphs paragraph [0025], [0027], and [0029]) configured to communicate binary signaling and multi-level signaling, wherein a multi-level signal of the multi-level signaling represents a plurality of bits of information (paragraphs [0024] and [0030]), wherein each channel of the plurality of channels is independent from other channels of the plurality of channels (paragraph [0039]), and wherein the plurality of channels comprise one or more unidirectional channels and one or more bidirectional channels; and a controller coupled with the array of memory cells via the interposer (Figs. 1-2, channels 124-125, CPU/GPU 102, paragraphs [0023] and [0025]-[0029]), the controller configured to cause the memory device to: identify, by the controller, information to be communicated/routed to an array of memory cells (Figs. 1-2, CPU/GPU (controller) 102, memory cells 110, 114, and 116, paragraph [0025] and [0027]); and transmit, by the controller via the interposer, a signal to the array of memory cells, wherein the signal is transmitted across one or more channels of the plurality of channels included in the interposer (Figs. 1-2, CPU/GPU 102, channels 124-125, interposer 120, array of memory cells 112, 114, and 116, paragraphs [0025]-[0028]).
Nygren does not expressly teach identifying, by a controller of a memory device, data to be written to an array of memory cells.
Jeong further teaches identifying, by a controller of a memory device, data to be written to an array of memory cells (Figs. 1-2, paragraphs [0025], [0027]-[0028], and [0034]).
It would have been obvious to one of ordinary skill in the art to identify, by a controller of a memory device, data to be written to an array of memory cells in order for the apparatus to have its intended use such as reading signals from and writing signals to memory cells.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nygren in view of Shoemaker et al. (hereinafter referred to as “Shoemaker”, US 9,627,357).
As to claim 7, Nygren teaches a substrate coupled with the interposer (Fig. 1, substrate 130, interposer 120).
Nygren does not expressly teach that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material.
Shoemake further teaches that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material (Fig. 3B, silicon interposer 382, non-silicon substrate 384).
It would have been obvious to one of ordinary skill in the art that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material depending on the design requirements and/or goal. For example, non-silicon substrates are ideal for high-power, high-temperature, and high-frequency applications, whereas silicon substrates and/or interposers have high thermal conductivity, low cost, and mechanical flexibility.
Claim(s) 15 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nygren in view of Jeong, and further in view of Shoemaker.
As to claims 15 and 21, Nygren teaches a substrate coupled with the interposer (Fig. 1, substrate 130, interposer 120).
Nygren and Jeong do not expressly teach that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material.
Shoemake further teaches that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material (Fig. 3B, silicon interposer 382, non-silicon substrate 384).
It would have been obvious to one of ordinary skill in the art that the substrate comprising a first material, wherein the interposer comprises a second material that is different than the first material depending on the design requirements and/or goal. For example, non-silicon substrates are ideal for high-power, high-temperature, and high-frequency applications, whereas silicon substrates and/or interposers have high thermal conductivity, low cost, and mechanical flexibility.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRESHTEH N AGHDAM whose telephone number is (571)272-6037. The examiner can normally be reached Monday-Friday 10:30-7:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRESHTEH N AGHDAM/Primary Examiner, Art Unit 2632 7/11/2026
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