DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,237,831. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain substantially similar subject matter (see chart below).
Claims 2-8, 10-14 and 16-20 are also rejected as being dependent on claims 1, 9, 15 and may also correspond to claims 2-5, 7-11 and 13-16 of the ‘831 patent.
Instant Application
US Patent No. 12,237,831
1. A multi-die system, comprising: a processing circuit disposed on a first die; and a network-on-chip disposed at least in part on the first die, wherein the network- on-chip is configurable to facilitate memory transactions between the first die and a second die, wherein the network-on-chip comprises a plurality of data channels, wherein a first subset of data channels of the plurality of data channels are configurable to transmit data between portions of the processing circuit via the network-on-chip, and wherein a second subset of data channels of the plurality of data channels are configurable to transmit data between the first die and the second die.
1. A multi-die system, comprising: a processing circuit disposed on a first die; and a network-on-chip disposed at least in part on the first die, wherein the network-on-chip is configurable to facilitate memory transactions between the first die and a second die, wherein the network-on-chip comprises a plurality of data lanes (channels), wherein the network-on-chip is configurable to transmit data between the first die and the second die via a bus formed from the plurality of data lanes (channels), and wherein the network-on-chip is configurable to reduce power consumed at least in part by reducing a width of the bus based on traffic latency and bandwidth.
4. The multi-die system of claim 1, wherein the network-on-chip comprises a first set (subset) of data lanes (channels) of the plurality of data lanes and a second set (subset) of data lanes (channels) of the plurality of data lanes.
9. A method, comprising: operating a programmable interconnect network at a first data width, wherein the programmable interconnect network is configurable to span multiple die of a same package; reprogramming a first data channel of the programmable interconnect network; and operating a subset of the programmable interconnect network at a second data width lower than the first data width, wherein the second data width excludes a width of the first data channel.
6. A method, comprising: operating a programmable interconnect network at a first data width, wherein the programmable interconnect network is configurable to span multiple die of a same package; determining, (reprogramming) based on memory latency, to reduce a power state of the programmable interconnect network; and reducing the power state of the programmable interconnect network at least in part by operating the programmable interconnect network at a second data width less than (lower) the first data width.
15. An integrated circuit, comprising: a first set of channels of a plurality of channels of a network-on-chip; and a second set of channels of the plurality of channels, wherein the second set of channels and the first set of channels are configurable to facilitate communication between a first die and a second die.
12. An integrated circuit, comprising: a first set of lanes (channels) of a plurality of lanes corresponding to a network-on-chip; and a second set of lanes (channels) of the plurality of lanes corresponding to the network-on-chip, wherein the second set of lanes (channels) and the first set of lanes are configurable to facilitate memory transactions (communication) between a first die and a second die, and wherein using the first set of lanes to transmit data while the second set of lanes is inactive is based on memory latency and reduces power consumed by the network-on-chip.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Swarbrick et al. (US 2019/0266125).
In regards to claim 1, Swarbrick discloses of a multi-die system, comprising: a processing circuit (for example 410) disposed on a first die; and a network-on-chip (for example 105) disposed at least in part on the first die, wherein the network- on-chip (105) is configurable to facilitate memory transactions between the first die and a second die, wherein the network-on-chip (105) comprises a plurality of data channels, wherein a first subset of data channels of the plurality of data channels are configurable to transmit data between portions of the processing circuit (410) via the network-on-chip (105, see Fig 4), and wherein a second subset of data channels of the plurality of data channels are configurable to transmit data between the first die and the second die (for example between 405A-B via 105, see Fig 4).
In regards to claim 2, Swarbrick discloses of the multi-die system of claim 1, wherein the second subset of data channels is configured to couple to the second die via an interface block (see Fig 4).
In regards to claim 3, Swarbrick discloses of the multi-die system of claim 1, wherein the processing circuit comprises programmable logic fabric (see Paragraph 0026).
In regards to claim 4, Swarbrick discloses of the multi-die system of claim 3, wherein the first subset of data channels is configured to enable communications between a first portion of the programmable logic fabric and a second portion of the programmable logic fabric (for example see Fig 4).
In regards to claim 5, Swarbrick discloses of the multi-die system of claim 1, wherein the network-on-chip is configurable to reduce power consumed at least in part by reducing a width of a bus formed based on the plurality of data channels based on traffic latency and bandwidth (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress which would result in power conservation).
In regards to claim 6, Swarbrick discloses of the multi-die system of claim 1, wherein the network-on-chip is configurable to reduce power consumed at least in part by reducing a width of a bus formed based on the plurality of data channels based on memory latency (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress which would result in power conservation).
In regards to claim 7, Swarbrick discloses of the multi-die system of claim 1, wherein the second subset of data channels is configured to receive data associated with a memory transaction (for example via 415) of the second die (for example see Fig 4 and Paragraphs 0039-0044).
In regards to claim 8, Swarbrick discloses of the multi-die system of claim 1, wherein the plurality of data channels comprises four data channels, and wherein the second subset of data channels comprises one of the four data channels (for example see Fig 4).
In regards to claim 9, Swarbrick discloses of a method, comprising: operating a programmable interconnect network at a first data width, wherein the programmable interconnect network is configurable to span multiple die of a same package (for example see Fig 4); reprogramming a first data channel of the programmable interconnect network; and operating a subset of the programmable interconnect network at a second data width lower than the first data width, wherein the second data width excludes a width of the first data channel (see Paragraphs 0037-0038, 0042, 0052 with respect to the data width adjustments).
In regards to claim 10, Swarbrick discloses of the method of claim 9, comprising determining to reduce a power state of the programmable interconnect network at least in part by determining to repurpose the first data channel of the programmable interconnect network (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress which would result in power conservation).
In regards to claim 11, Swarbrick discloses of the method of claim 10, comprising reducing the power state of the programmable interconnect network at least in part by operating the subset of the programmable interconnect network at the second data width lower than the first data width (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress which would result in power conservation).
In regards to claim 12, Swarbrick discloses of the method of claim 9, comprising determining to repurpose the first data channel of the programmable interconnect network based on memory latency (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress).
In regards to claim 13, Swarbrick discloses of the method of claim 9, comprising determining to repurpose the first data channel of the programmable interconnect network based on traffic latency and bandwidth (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress).
In regards to claim 14, Swarbrick discloses of the method of claim 9, comprising: generating a data packet associated with a memory transaction (for example via 415); and sending the data packet via the first data channel (see Fig 4 and Paragraphs 0039-0044).
In regards to claim 15, Swarbrick discloses of an integrated circuit, comprising: a first set of channels of a plurality of channels of a network-on-chip (104); and a second set of channels of the plurality of channels, wherein the second set of channels and the first set of channels are configurable to facilitate communication between a first die and a second die (for example see Fig 4 and Paragraphs 0039-0042).
In regards to claim 16, Swarbrick discloses of the integrated circuit of claim 15, wherein, for a first communication, the second set of channels are configured to transmit data between the first die and second die (for example see Fig 4).
In regards to claim 17, Swarbrick discloses of the integrated circuit of claim 16, wherein, for a second communication, the second set of channels are configured to be used with the first set of channels to transmit data between a first portion of circuitry of the first die and a second portion of circuitry of the first die (see Fig 4).
In regards to claim 18, Swarbrick discloses of the integrated circuit of claim 17, wherein using the second set of channels with the first set of channels for the second communication is determined based on memory latency (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress).
In regards to claim 19, Swarbrick discloses of the integrated circuit of claim 16, wherein the first communication corresponds to a memory transaction (for example via 415) associated with a memory disposed external to the network-on-chip (104, see Fig 4 and Paragraphs 0039-0044).
In regards to claim 20, Swarbrick discloses of the integrated circuit of claim 16, wherein using the second set of channels separate from the first set of channels for the first communication is determined based on traffic latency and bandwidth (for example see Paragraphs 0031-0052, adjustments made with regards to frequency, traffic with respective to its ingress and egress).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M CRAWFORD/Primary Examiner, Art Unit 2844
Prosecution Insights