Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,007,918.
Although the claims at issue are not identical, they are not patentably distinct from each other because both disclose “a performance analyzer configured to measure/calculate throughputs of …functions,” a traffic class controller configured to allocate traffic class values to transaction layer packets received from the plurality of functions based on the throughputs of the plurality of functions”, and further the traffic class controller “..reallocate the traffic class values of the transaction layer packets based on the varied ranking.”
Claims 1-21 are rejected on the ground of provisional nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent 12,007,918. Specifically, claims 1, 4, and 16 of 19/029,531.
Instant Application Claim 1, 19/029,531
Claim 1, US Patent 12,007,918
A Peripheral Component Interconnect Express (PCIe) interface device, comprising: a performance analyzer configured to calculate throughput of a function by counting a number of transaction layer packets transferred between a direct memory access device and a host system; and
a traffic class controller configured to allocate a traffic class value to the function based on data received from the performance analyzer wherein the data includes the throughput of the function, and
wherein the traffic class value indicates priority of the transaction layer packets processed by the function..
A Peripheral Component Interconnect Express (PCIe) interface device, comprising: a performance analyzer configured to calculate throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices by counting a number of transaction layer packets transferred between the one or more DMA devices and a host system per unit time; and a traffic class controller configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions, and to reallocate the traffic class values of the transaction layer packets when rankings of the throughputs of the multiple functions are changed, wherein the traffic class values indicate virtual channels which the transaction layer packets are mapped.
CLAIM 4. The PCIe interface device according to
claim 1, wherein the traffic class controller is
configured to, whenever a ranking of the
throughput of the function varies, reallocate
the traffic class value of the function based on
the varied ranking.
CLAIM 16. A Peripheral Component
Interconnect Express (PCIe) device, comprising: a
performance analyzer configured to measure
throughputs of a plurality of functions executed
on one or more direct memory access devices;
a write buffer configured to store a plurality of
first transaction layer packets received from
the plurality of functions; a read buffer
configured to store a plurality of second
transaction layer packets received from the
plurality of functions; and a buffer controller
configured to, when a write buffer of a switch
is full, realign an order in which the plurality
of second transaction layer packets are to be
output from the read buffer to a read buffer of
the switch, based on IDs of the plurality of
second transaction layer packets.
CLAIM 17. The method according to claim
15, wherein allocating the different traffic
class values to the transaction layer packets
comprises:
allocating a ranking of traffic class values
to transaction layer packets received
from functions for which throughputs are
less than or equal to the threshold value,
among the multiple functions, in a
reverse order of a ranking of the
throughputs of the multiple functions.
CLAIM 18. (Previously Presented) The
method according to claim 12, wherein
the virtual channels are determined by a
switch or a root complex depending on
the traffic class values allocated to the
transaction layer packets, and an order in
which the transaction layer packets are to
be output is determined by the switch or
the root complex based on the virtual
channels mapped to the transaction layer
packets.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tammara Peyton whose telephone number is (571) 272-4157. The examiner can normally be reached between 8:30- 6:00 from Monday to Thursday, (I am off every first Friday), and 7:30- 4:00 every second Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Henry Tsai can be reached on (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Any inquiry of a general nature of relating to the status of this application should be directed to the Group receptionist whose telephone number is (571) 272- 2100.
/Tammara R Peyton/
Primary Examiner, Art Unit 2184
August 22, 2026
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