Prosecution Insights
Last updated: July 17, 2026
Application No. 19/029,600

System and Method For Interconnected Elements of a Power System

Non-Final OA §DOUBLEPATENT
Filed
Jan 17, 2025
Priority
May 30, 2017 — provisional 62/512,218 +3 more
Examiner
AMAYA, CARLOS DAVID
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Solaredge Technologies Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
903 granted / 1078 resolved
+15.8% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1078 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-2, 7-10, 12-13, 16-18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, 12, 17 of U.S. Patent No. 10,931,104. Although the claims at issue are not identical, they are not patentably distinct from each other because. With respect to claim 1, claim 1 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 1. With respect to claim 2, claim 1 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 2. With respect to claim 7, claim 1 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 7. With respect to claim 8, claim 12 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 8. With respect to claim 9, claim 12 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 9. With respect to claim 10, claim 17 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 10. With respect to claim 12, claim 8 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 12. With respect to claim 13, claim 12 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 13. With respect to claim 16, claim 1 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 16. With respect to claim 17, claim 12 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 17. With respect to claim 18, claim 12 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 18. With respect to claim 20, claim 8 of U.S. Patent No. 10,931,104 discloses all the limitations of claim 20. Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 10,931,104 in view of Adest et al (US 2012/0139343) (“Adest”). With respect to claim 3, claim 1 of U.S. Patent No. 10,931,104 discloses claim 3; except for, a plurality of bypass diodes, each bypass diode connected to a corresponding power source of the second group of power sources and configured to, in the first state, bypass the corresponding power source of the second group of power sources. Adest discloses a plurality of devices 405 connected to respective power sources, each of the devices comprise a bypass diode 414, figure 4A. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claim invention, to have modify U.S. Patent No. 10,931,104 and include the bypass diodes of Ades, for the purpose of having a bypass route that carries the current and prevents the source from becoming a sink, for example (paragraph 0006). Allowable Subject Matter Claims 4-6, 11, 14-15,19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 is allowable over the prior art of record, because the prior art of record does not disclose a second plurality of switches, each switch of the second plurality of switches connected to a corresponding power source of the second group of power sources, and wherein the controller is further configured to: in the first state, bypass the one or more power sources of the second group of power sources by controlling one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources. Claim 5 is allowable over the prior art of record, because the prior art of record does not disclose a second plurality of switches, each switch of the second plurality of switches connected to a corresponding power source of the second group of power sources, and wherein the controller is further configured to: in the second state, allow the one or more power sources of the second group of power sources to connect to the first group of power sources by controlling one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources. Claim 6 is allowable over the prior art of record, because the prior art of record does not disclose a second plurality of switches, each switch of the second plurality of switches connected to a corresponding power source of the second group of power sources, and wherein the controller is further configured to: reduce a voltage across the one or more power sources of the second group of power sources by controlling one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources. Claim 11 is allowable over the prior art of record, because the prior art of record does not disclose wherein the system power device is configured to perform at least one of: signaling, based on an input current to the system power device being below a threshold, the device to operate one or more switches of the plurality of switches in the first state; or signaling, based on the input current to the system power device being above the threshold, the device to operate the one or more switches of the plurality of switches in the second state. Claim 14 is allowable over the prior art of record, because the prior art of record does not disclose wherein the device further comprises a second plurality of switches, each switch of the second plurality of switches connected to a corresponding power source of the second group of power sources, and the method further comprising: bypassing the one or more power sources of the second group of power sources by controlling one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources, to be in the first state; and connecting the one or more power sources of the second group of power sources to the first group of power sources by controlling the one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources, to be in the second state. Claim 15 is allowable over the prior art of record, because the prior art of record does not disclose wherein the device further comprises a second plurality of switches, each switch of the second plurality of switches connected to a corresponding power source of the second group of power sources, and wherein the method further comprises: reducing a voltage across the one or more power sources of the second group of power sources by controlling one or more switches, of the second plurality of switches, respectively corresponding to the one or more power sources. Claim 19 is allowable over the prior art of record, because the prior art of record does not disclose receiving, by the device and from a system power device, the one or more signals, wherein the system power device is configured to signal the device to perform at least one of: based on an input current to the system power device being below a threshold, operating one or more switches of the plurality of switches in the first state; or based on the input current to the system power device being above the threshold, operating the one or more switches of the plurality of switches in the second state. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS AMAYA whose telephone number is (571)272-8941. The examiner can normally be reached M-F 7:00AM-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at (571) 272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CARLOS AMAYA/Primary Examiner, Art Unit 2836
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Prosecution Timeline

Jan 17, 2025
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §DOUBLEPATENT
Jul 07, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+13.7%)
2y 6m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1078 resolved cases by this examiner. Grant probability derived from career allowance rate.

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