Prosecution Insights
Last updated: October 25, 2026
Application No. 19/029,740

DETECTING MICROCRACKS IN A SEMICONDUCTOR DIE

Non-Final OA §102§103
Filed
Jan 17, 2025
Examiner
LIN, ERICA S Y
Art Unit
2853
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
931 granted / 1083 resolved
+18.0% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
18.7%
-21.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1083 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 6-9, 16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Pub. 2013/0077650 (“Traxler”). Claim 1 Traxler discloses a method, comprising: applying an electrical current to a semiconductor die (paragraph [0046], induction coil 112); thermally scanning an area of the semiconductor die for one or more thermal variations (paragraph [0050], heat sensitive camera 120); generating a heat map based, at least in part, on the one or more thermal variations (paragraph [0050], thermographic image); analyzing the heat map to determine whether any of the one or more thermal variations exceeds a thermal variation threshold (paragraphs [0056-0058], image analysis); and identifying a microcrack based, at least in part, on a determination that at least one thermal variation exceeds the thermal variation threshold (paragraph [0057], crack identification). Claim 6 Traxler discloses the method of claim 1, wherein the thermal variations are identified based, at least in part, by comparing a temperature reading to a baseline temperature (paragraph [0060], comparison of measurement over time). Claim 7 Traxler discloses the method of claim 1, wherein thermally scanning the area of the semiconductor die for the one or more thermal variations comprises: positioning at least one thermal sensor above the semiconductor die; causing the thermal sensor to scan the area; and collecting thermal data across the scanning area (paragraph [0050-0055]). Claim 8 Traxler discloses the method of claim 1, wherein applying the electrical current to the semiconductor die comprises applying the electrical current to a connector associated with the semiconductor die (induction coil 112). Claim 9 Traxler discloses the method of claim 1, wherein the thermal scanning is complete in four seconds or less (Fig. 5). Claim 16 Traxler discloses a system, comprising: means for inducing localized heating of a semiconductor die (paragraph [0046], induction coil 112); means for measuring a surface temperature the semiconductor die (paragraph [0050], heat sensitive camera 120); means for generating a heat map based, at least in part, on the surface temperature of the semiconductor die (paragraph [0050], thermographic image); and means for analyzing the heat map to detect a crack within the at least one memory die (paragraphs [0056-0058], image analysis). Claim 18 Traxler discloses the system of claim 16, wherein the means for measuring the surface temperature of the semiconductor die comprise at least one thermal sensor (Traxler, paragraph [0050], heat sensitive camera 120) Claim 20 Traxler discloses the system of claim 16, wherein the crack is detected based, at least in part, on a comparison between a temperature reading of an area of the semiconductor die to a baseline temperature (paragraph [0060], comparison of measurement over time). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-5, 10-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2013/0077650 (“Traxler”) in view of U.S. Patent Pub. 2006/0137466 (“Wright”). Claim 2 Traxler discloses the method of claim 1. Traxler does not appear to explicitly disclose wherein applying the electrical current to the semiconductor die comprises: positioning a plurality of probes on the semiconductor die; and providing the electrical current to the plurality of probes. Wright discloses a method of crack growth testing by passing current through a test specimen (paragraph [0008-0009, 0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein applying the electrical current to the semiconductor die comprises: positioning a plurality of probes on the semiconductor die; and providing the electrical current to the plurality of probes, as disclosed by Wright, into the method of Traxler, for the purpose of determining component lifetime (Wright, paragraphs [0006-0007]). Claim 3 Traxler in view of Wright discloses the method of claim 2, wherein positioning the plurality of probes on the semiconductor die comprises positioning a first probe of the plurality of probes at a first location on the semiconductor die and positioning a second probe of the plurality of probes at a second location on the semiconductor die, the second location being different than the first location (Wright, paragraphs [0008-0009]). Claim 4 Traxler in view of Wright discloses the method of claim 3, wherein the first location comprises a corner of the semiconductor die and the second location comprises a center of the semiconductor die (Wright, Fig. 2A). Claim 5 Traxler in view of Wright discloses the method of claim 2, wherein the electrical current is in a range between ten microamps (µA) and one hundred µA (Wright, paragraph [0024]). Claim 10 Traxler discloses a method, comprising: providing an electrical current through the plurality of probes to induce localized heating of the at least one semiconductor die (paragraph [0046], induction coil 112); removing the plurality of probes from the at least one semiconductor die (Fig. 1); scanning a scanning area of the at least one semiconductor die to collect thermal data associated with the scanning area (paragraph [0050], heat sensitive camera 120); generating a heat map based, at least in part, on the thermal data (paragraph [0050], thermographic image); and analyzing the heat map to detect thermal variations that exceed a thermal variation threshold value to detect a microcrack (paragraph [0057], crack identification). Traxler does not appear to explicitly disclose positioning a plurality of probes on at least one semiconductor die. Wright discloses a method of crack growth testing by passing current through a test specimen (paragraph [0008-0009, 0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated positioning a plurality of probes on at least one semiconductor die, as disclosed by Wright, into the method of Traxler, for the purpose of determining component lifetime (Wright, paragraphs [0006-0007]). Claim 11 Traxler in view of Wright discloses the method of claim 10, wherein generating the heat map comprises generating a visual representation of the collected thermal data with a precision of five microns (Wright, paragraph [0031], less than 17 mm). Claim 12 Traxler in view of Wright discloses the method of claim 11, wherein the precision of five microns facilitates detection of internal cracks as small as ten microns (Wright, paragraph [0031], less than 17 mm). Claim 13 Traxler discloses the method of claim 10. Traxler does not appear to explicitly disclose wherein the electrical current is in a range between ten microamps (µA) and one hundred µA. Wright discloses a method of crack growth testing by passing current through a test specimen between ten microamps (µA) and one hundred µA (paragraph [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the electrical current is in a range between ten microamps (µA) and one hundred µA, as disclosed by Wright, into the method of Traxler, for the purpose of determining component lifetime (Wright, paragraphs [0006-0007]). Claim 14 Traxler in view of Wright discloses the method of claim 10, wherein the thermal variations are identified based, at least in part, by comparing a temperature reading to a baseline temperature (Traxler, paragraph [0060], comparison of measurement over time). Claim 15 Traxler in view of Wright discloses the method of claim 10, wherein positioning the plurality of probes on the at least one semiconductor die comprises positioning a first probe of the plurality of probes proximate an edge of the at least one semiconductor die and positioning a second probe of the plurality of probes proximate a center of the at least one semiconductor die (Wright, paragraphs [0008-0009]). Claim 17 Traxler in view of Wright discloses he system of claim 16. Traxler does not appear to explicitly disclose wherein the means for inducing localized heating of the semiconductor die comprise a plurality of conductive probes (Fig. 1). Wright discloses a method of crack growth testing by passing current through a test specimen and conductive probes (Fig. 2A, paragraph [0008-0009, 0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the means for inducing localized heating of the semiconductor die comprise a plurality of conductive probes, as disclosed by Wright, into the method of Traxler, for the purpose of determining component lifetime (Wright, paragraphs [0006-0007]). Claim 19 Traxler discloses the system of claim 16. Traxler does not appear to explicitly disclose wherein the means for analyzing the heat map to detect a crack within the semiconductor die detects cracks as small as ten microns. Wright discloses a method of crack growth testing by passing current through a test specimen (Wright, paragraph [0031], less than 17 mm). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the means for analyzing the heat map to detect a crack within the semiconductor die detects cracks as small as ten microns, as disclosed by Wright, into the method of Traxler, for the purpose of determining component lifetime (Wright, paragraphs [0006-0007]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERICA S Y LIN whose telephone number is (571)270-7911. The examiner can normally be reached M-F 8-4, TW M,W. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERICA S LIN/Primary Examiner, Art Unit 2853
Read full office action

Prosecution Timeline

Jan 17, 2025
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12767524
ENHANCED MEMS SENSOR EMBEDDED HEATER
5y 1m to grant Granted Oct 20, 2026
Patent 12768728
AUTOMATIC CALIBRATION FOR BACKSCATTERING-BASED DISTRIBUTED TEMPERATURE SENSOR
2y 7m to grant Granted Oct 20, 2026
Patent 12761098
APPARATUS AND PROCESS FOR DETECTING A LEAK DURING ARTIFICIAL VENTILATION
3y 0m to grant Granted Oct 13, 2026
Patent 12761085
RESPONSE OF HEAT DETECTORS WITH SURFACE MOUNTED THERMISTORS
2y 10m to grant Granted Oct 13, 2026
Patent 12754074
Infrared Sensor Mounting System for Low-Voltage Switchgear
2y 11m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+2.7%)
2y 3m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1083 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month