DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Response to Arguments
Applicant's arguments filed 06/25/2026 have been fully considered but they are not persuasive.
Applicant argues: (1) the combination of Kahle and Fuller relies on impermissible hindsight and non-analogous arts [remarks, pp. 8-9]; (2) incorporating Fuller into Kahle is physical unworkable and would destroy Kahle’s principle of operation [remarks, pp. 8-9]; (3) the proposed combination improperly conflates the macro-level “tasks” of Fuller with micro-level “instructions” of the claimed method [remarks, p. 9].
The examiner respectfully disagrees with these arguments.
Regarding the first argument, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument that Fuller is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The examiner also notes that the determination of what arts are analogous to a particular claimed invention “depends upon the necessary essential function or utility of the subject matter covered by the claims, and not upon what it is called by the applicant. For example, for search purposes, a tea mixer and a concrete mixer may both be regarded as relating to the mixing art, this being the necessary function of each. Similarly a brick-cutting machine and a biscuit cutting machine may be considered as having the same necessary function” [MPEP 904.01(c)]. In this case, claims 10-11 and 19-20 recite the essential function or utility of a queue with a first block (comprising at least one instruction) and deleting the first block from the queue when the execution status of all instructions are a completed state. Fuller has the same necessary function of implementing a queue with an instruction and deleting the instructions from the queue when the execution statuses are a completed state [Fuller, col. 12, lines 18-29, “Server 106 deletes (538) all of the tasks in the first group from the primary task queue. In some embodiments, the batch delete instruction is sent by the first worker process when the first worker process has completed processing of the tasks in the first portion”]. In addition, both the claimed invention and Fuller are related to the instruction queuing art, hence Fuller is in the field of the inventor’s endeavor.
Lastly, applicant argues that a “person of ordinary skill in the art of microprocessor architecture and hardware-level instruction processing would not look to distributed client-server network task scheduling to modify a hardware completion table. The combination of such disparate fields to arrive at the claimed method is improper” [remarks, p. 8]. However, the examiner notes that it has been held that “[w]hen more than one prior art reference is used as the basis of an obviousness rejection, it is not required that the references be analogous art to each other”. See Sanofi-Aventis Deutschland GMbH v. Mylan Pharms. Inc., 66 F.4th 1373, 1380, 2023 USPQ2d 552 (Fed. Cir. 2023) and Corephotonics, Ltd. v. Apple Inc., 84 F.4th 990, 1007, 2023 USPQ2d 1202 (Fed. Cir. 2023) [MPEP 2141.01(a), I.]
Regarding the second argument, applicant argues that “[f]orcing a software-based ‘batch delete instruction’ from a web server environment into Kahle's high-speed, hardware completion pointer mechanism is technically incompatible and would destroy the efficient hardware logic that Kahle seeks to achieve. Thus, the proposed combination cannot be sustained” [remarks, pp. 8-9]. However, the examiner notes that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant’s argument is centered on bodily incorporating the prior art references, however bodily incorporation is not the test for obviousness.
Regarding the third argument, the examiner notes that applicant’s Specification is optionally directed towards a “task” [paragraph 140, “Optionally, this application is applied to a general-purpose out-of-order processor, or may be extended to a multi-core system as a hierarchical solution for recording statuses of a plurality of tasks”]. Hence, the examiner has not improperly conflated tasks with instructions and therefore maintains the obviousness rejection.
In regard to claims 11, 14, and 16-18, applicant has not provided specific arguments as to how said claims patentably distinguish themselves them from the references. Therefore, the prior art rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 10-11, 14, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kahle et al (hereinafter Kahle), US 6654869 B1, in view of Fuller, US 8826284 B1.
Referring to claims 1, 10, and 19, taking claim 1 as exemplary, Kahle discloses an instruction execution method, wherein the method comprises:
determining that an execution status of a first block in a queue [fig. 3, element 306] is a completed state [col. 5, lines 25-30, lines 41-44, “In addition, dispatch unit 114 communicates with dispatch and completion control logic 116 to keep track of the order in which instructions were issued and the completion status of these instructions to facilitate out-of-order execution”; “In association with dispatch and completion control logic 116, a completion table 118 is utilized in one embodiment of the present invention to track the status of issued instruction groups”], wherein the queue comprises a plurality of blocks comprising the first block [fig. 3], the first block is a block with a smallest number in the queue [col. 5, lines 30-40, “In the embodiment of processor 100 in which cracking unit 112 organizes incoming instructions into instruction groups as discussed above, each instruction group 202 is assigned a group tag (GTAG) by completion and control logic 116 that conveys the ordering of the issued instruction groups. As an example, dispatch unit 114 may assign monotonically increasing values to consecutive instruction groups”; “With this arrangement, instruction groups with lower GTAG values are known to have issued prior to (i.e., are younger than) instruction groups with larger GTAG values”; hence, an instruction group that issued prior to other instruction groups will have the smallest number in the queue], and the first block comprises at least one instruction [col. 3, lines 44-48, “The organization of a set of instructions into instruction groups facilitates high speed execution by, among other things, simplifying the logic needed to maintain completion tables for a large number of in-flight instructions”];
changing a status of a processor based on an execution result of the at least one instruction in the first block [col. 6, lines 29-38, “A mapping is maintained between the rename GPRs and their corresponding architected registers. When all instructions in an instruction group (and all instructions in younger instruction groups) finish without generating an exception, a completion pointer in the completion table 218 is incremented to the next instruction group. When the completion pointer is incremented to a new instruction group, the rename registers associated with the instructions in the old instruction group are released thereby committing the results of the instructions in the old instruction group”].
Kahle does not explicitly disclose deleting the first block from the queue.
However, Fuller discloses deleting the first block from the queue [col. 12, lines 18-29, “a batch delete instruction to delete all of the tasks in the first group from the primary task queue and in response to the batch delete instruction, Server 106 deletes (538) all of the tasks in the first group from the primary task queue. In some embodiments, the batch delete instruction is sent by the first worker process when the first worker process has completed processing of the tasks in the first portion”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fuller, in the method of Kahle, to implement deleting the first block from the queue, in order to scalably and efficiently schedule tasks in a manner that avoids bottlenecks and reduces latency [Fuller, col. 1, lines 41-43].
Referring to claims 2, 11, and 20, taking claim 2 as exemplary, the modified Kahle discloses the method according to claim 1, wherein the determining that an execution status of a first block in a queue is a completed state comprises:
determining that execution statuses of all instructions comprised in the first block are a completed state [Kahle, col. 5, lines 25-30, lines 41-44, “In addition, dispatch unit 114 communicates with dispatch and completion control logic 116 to keep track of the order in which instructions were issued and the completion status of these instructions to facilitate out-of-order execution”; “In association with dispatch and completion control logic 116, a completion table 118 is utilized in one embodiment of the present invention to track the status of issued instruction groups”].
Referring to claims 5 and 14, taking claim 5 as exemplary, the modified Kahle discloses the method according to claim 1, wherein the method further comprises:
obtaining one or more third blocks, wherein each of the one or more third blocks comprises at least one instruction [Kahle; col. 5, lines 30-40, “In the embodiment of processor 100 in which cracking unit 112 organizes incoming instructions into instruction groups as discussed above, each instruction group 202 is assigned a group tag (GTAG) by completion and control logic 116 that conveys the ordering of the issued instruction groups. As an example, dispatch unit 114 may assign monotonically increasing values to consecutive instruction groups”; “With this arrangement, instruction groups with lower GTAG values are known to have issued prior to (i.e., are younger than) instruction groups with larger GTAG values”; hence, an instruction group that issued prior to other instruction groups will have the smallest number in the queue], and the first block comprises at least one instruction [col. 3, lines 44-48, “The organization of a set of instructions into instruction groups facilitates high speed execution by, among other things, simplifying the logic needed to maintain completion tables for a large number of in-flight instructions”]; and
placing the one or more third blocks in the queue in ascending order of numbers [Kahle; col. 5, lines 30-40, “In the embodiment of processor 100 in which cracking unit 112 organizes incoming instructions into instruction groups as discussed above, each instruction group 202 is assigned a group tag (GTAG) by completion and control logic 116 that conveys the ordering of the issued instruction groups. As an example, dispatch unit 114 may assign monotonically increasing values to consecutive instruction groups”], and the first block comprises at least one instruction [col. 3, lines 44-48, “The organization of a set of instructions into instruction groups facilitates high speed execution by, among other things, simplifying the logic needed to maintain completion tables for a large number of in-flight instructions”].
Claim(s) 7-8 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kahle, in view of Fuller, as applied to claims 1 and 10 above, and further in view of Le et al (hereinafter Le), US 6721874 B1.
Referring to claims 8 and 17, taking claim 8 as exemplary, the modified Kahle does not explicitly disclose the method according to claim 1, wherein the method further comprises:
obtaining an interruption signal; and deleting an instruction other than an instruction with a smallest number from the queue.
However, Le discloses obtaining an interruption signal; and
deleting an instruction other than an instruction with a smallest number from the queue [col. 8, lines 23-41, “When an exception condition such as branch misprediction or interrupt is encountered, all speculative groups of instruction that were dispatched after the instructions that encounter the exception condition need be discarded (flushed)”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Le, in the method of the modified Kahle, to implement obtaining an interruption signal; and deleting an instruction other than an instruction with a smallest number from the queue, in order to provide an improved processor architecture that efficiently implements completion status [Le, col. 2, lines 8-17].
Referring to claims 7 and 16, taking claim 7 as exemplary, the modified Kahle does not explicitly disclose the method according to claim 1, wherein the method further comprises:
obtaining an abnormal signal and an abnormal instruction number; and
deleting, from the queue, an instruction whose instruction number is greater than or equal to the abnormal instruction number.
However, Le discloses obtaining an abnormal signal and an abnormal instruction number [col. 8, lines 23-41, “When an exception condition such as branch misprediction or interrupt is encountered, all speculative groups of instruction that were dispatched after the instructions that encounter the exception condition need be discarded (flushed)”]; and
deleting, from the queue, an instruction whose instruction number is greater than or equal to the abnormal instruction number [col. 8, lines 23-41, “In a superscalar machine, several instructions belonging to several different groups can encounter the exception condition simultaneously. Each execution unit reports the exception condition by sending a GTAG associated with the group that needs to be flushed to a completion function”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Le, in the method of the modified Kahle, to implement obtaining an abnormal signal and an abnormal instruction number; and deleting, from the queue, an instruction whose instruction number is greater than or equal to the abnormal instruction number, in order to provide an improved processor architecture that efficiently implements completion status [Le, col. 2, lines 8-17].
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kahle, in view of Fuller, as applied to claims 1 and 10 above, and further in view of Cheong et al (hereinafter Cheong), US 5974524.
Referring to claims 9 and 18, taking claim 9 as exemplary, the modified Kahle discloses the method according to claim 1, wherein the method further comprises:
when execution of a third instruction is completed, setting an execution status of the third instruction to a completed state, wherein the third instruction is in the queue [Kahle, col. 5, lines 25-30, lines 41-44, “In addition, dispatch unit 114 communicates with dispatch and completion control logic 116 to keep track of the order in which instructions were issued and the completion status of these instructions to facilitate out-of-order execution”; “In association with dispatch and completion control logic 116, a completion table 118 is utilized in one embodiment of the present invention to track the status of issued instruction groups”].
Kahle does not explicitly disclose or when an exception occurs during execution of the third instruction, setting the execution status of the third instruction to an abnormal state.
However, Cheong discloses when an exception occurs during execution of the third instruction, setting the execution status of the third instruction to an abnormal state [col. 6, lines 11-36, “The execution unit 150 is designed, according to known techniques, to detect whether the instruction completes without generating an exception due to an error condition. When the execution unit 150 finishes operating on the instruction, it generates a finish report. The finish report indicates to other resources on the processor whether the instruction was satisfactorily executed by the execution unit 150, or whether an error condition arose requiring the generation of an exception”; “It will be noted that if there is an abnormal completion, then the status bits are used to indicate the type of abnormality. Different types of abnormalities may occur depending on the architecture used, and thus, the status indication will be largely a matter of design choice depending upon the architecture. Such status indication are known of those skilled in the art”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Cheong, in the method of the modified Kahle, to implement or when an exception occurs during execution of the third instruction, setting the execution status of the third instruction to an abnormal state, in order to improve out-of-order processing and increase parallel processing [Cheong, col. 2, lines 31-46].
Allowable Subject Matter
Claims 1-9 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest determining that a first piece is a commission piece in a second block of the plurality of blocks and an instruction in the first piece is in a completed state, wherein the second block is different from the first block, the first piece is one of a plurality of pieces comprised in the second block, the first piece comprises at least one instruction, the plurality of pieces in the second block are connected through tail pointers, and the commission piece is a piece that is in the second block and that starts to store an instruction earliest; and deleting the first piece from the second block, in combination with other recited limitations in claim 1.
Claims 2-9 are allowed based on their dependency.
Claims 12-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the logic circuit is configured to: determine that a first piece is a commission piece in a second block of the plurality of blocks and an instruction in the first piece is in a completed state, wherein the second block is different from the first block, the first piece is one of a plurality of pieces comprised in the second block, the first piece comprises at least one instruction, the plurality of pieces in the second block are connected through tail pointers, and the commission piece is a piece that is in the second block and that starts to store an instruction earliest; delete the first piece from the second block; and when the first piece is not a last piece in the second block, update the commission piece in the second block to a piece to which a tail pointer of the first piece points, in combination with other recited limitations in claim 12.
Claim 13 is objected to based on its dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the logic circuit is further configured to store an instruction in a fourth block into a second piece, wherein the fourth block is one of the one or more third blocks, and the second piece comprises at least one vacant location for storing an instruction, in combination with other recited limitations in claim 15.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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