The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 21-40 are presented for examination
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 and 17-21 of patent number 10725516. The table listed below shows the similarity between the two and highlight the differences.
Instant Application 19029831
Patent 10725516
21. (New) A semiconductor device comprising:
a first power source group including first and second power sources;
a second power source group including a third power source; and
a power sequence controller configured to perform power-on operations and power-off operations of the first to third power sources,
wherein the power sequence controller is configured to:
start a power-off operation of the first power source group at a first time,
start a power-off operation of the second power source group in response to a representative power supply voltage of the first power source group reaching a first reference voltage before a first reference time elapses since the first time, and
wherein the first reference voltage is greater than a power-off level of the first power source group.
(currently amended): A semiconductor device comprising:
a first power source group including first and second power sources;
a second power source group including a third power source; and
a power sequence controller configured to perform power-on operations and power-off operations of the first to third power sources,
wherein the power sequence controller is configured to start the power- off operation of the first power source group at a first time, and to start the power-off operation of the second power source group when a first reference time has passed from the first time,
wherein the power sequence controller is further configured to start the power-off operation of the second power source group when a power voltage of the first power source group drops to a first reference voltage before the first reference time has passed from the first time, and
wherein the first reference voltage is greater than a power-off level of the first power source group.
26. (New) The semiconductor device of claim 25, wherein the first reference voltage is greater than the second reference voltage.
27. (New) The semiconductor device of claim 25, wherein the first reference time is different from the second reference time.
28. (New) The semiconductor device of claim 21, wherein the representative power supply voltage of the first power source group is a power supply voltage output by the first power source or the second power source.
29. (New) The semiconductor device of claim 21, wherein the first power source and the second power source of the first power source group are adjacent to one other.
32. (New) The semiconductor device of claim 30, wherein the power sequence controller comprises a comparator configured to output a signal indicative of whether the representative power supply voltage of the first power source group has reached the first reference voltage.
4. (currently amended): The semiconductor device of claim 3, wherein the first reference voltage is different than from the second reference voltage.
5. (currently amended): The semiconductor device of claim 4, wherein the second reference voltage is greater than the first reference voltage.
6. (currently amended): The semiconductor device of claim 3, wherein the first reference time is different than from the second reference time.
8. (original): The semiconductor device of claim 1, wherein the power voltage of the first power source group is one of a power voltage of the first power source and a power voltage of the second power source.
9. (original): The semiconductor device of claim 8, wherein a power- off time of the first power source is greater than a power-off time of the second power source.
10. (currently amended): The semiconductor device of claim 1, wherein the power sequence controller further comprises a first comparator configured to detect whether the power voltage of the first power source group is the first reference voltage.
As shown from the table above, claims 1, 4-6, am 8-10 of patent 10725516 teaches the same concept of the instant application.
Conclusion
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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