DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2 – 6, 8 – 11, and 13 – 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 5, 8 – 10, and 13 – 20 of U.S. Patent No. 11455098. Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation of the instant claims has a similar corresponding limitation.
Instant Application 19/029863
US Patent 11455098
2. A method comprising: maintaining a memory map of a storage device having multiple types of volatile memory,
13. A method comprising: mapping volatile memory of a memory package at a host device; maintaining command latency information of a multiple volatile memory types of the memory package;
the memory map including command latency information for commands associated with each type of volatile memory of the multiple types of volatile memory;
maintaining command latency information of a multiple volatile memory types of the memory package;
1. … wherein the host device includes a memory map of the storage device and latency information associated with each command of the commands;…
sorting pending commands based on the command latency information; and
sorting pending commands according to a command latency associated with each of the volatile memory types of the multiple volatile memory types;
scheduling execution of the sorted pending commands by intermixing commands for a first type of volatile memory with commands for a second type of volatile memory to generate a command schedule,
intermixing commands for a first type of volatile memory and commands for a second type of volatile memory to provide a command schedule…
wherein execution of a first command for the first type of volatile memory has greater latency than execution of multiple serially issued commands for the second type of volatile memory.
wherein a latency of a command for the first type of volatile memory is greater than an accumulated latency of a multiple serially issued commands for the second type of volatile memory.
As shown above the main difference is that the instant claim specifies that the memory map includes the latency information. However, the US Patent has another claim, claim 1, that describes a memory map of the storage device and latency information. The combination of claims presented in the US Patent is therefore believed to obviously anticipate the instant claim.
Regarding claim 17 of the instant application, claim 1 of the US Patent is believed to obviously anticipate the claim language, similarly to what is presented above. The only difference is that the instant claim positively recites, “A host device comprising a processor configured to”. However, claim 1 of the US Patent describes, “a host device coupled to the storage device, the host device configured to issue commands to the storage device to store and retrieve information in the system.” A host device, as described in claim 1 of the US Patent would inherently include a processing element in order to issue commands and operate as claimed.
Claims 3 – 6, 8 – 11, 13 – 16, and 18 - 21 of the instant application are similarly obvious in view of claims 1 – 5, 8 – 10, and 13 – 20 of the US Patent.
Claims 2 – 6, 8 – 11, and 13 - 21 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 12, 14, and 17 – 18 of U.S. Patent No. 12216906. Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation of the instant claims has a similar corresponding limitation.
Instant Application 19/029863
US Patent 12216906
2. A method comprising: maintaining a memory map of a storage device having multiple types of volatile memory,
9. A method comprising: mapping volatile memory of a memory package at a host device; maintaining command latency information of multiple volatile memory types of the memory package;
the memory map including command latency information for commands associated with each type of volatile memory of the multiple types of volatile memory;
mapping volatile memory of a memory package at a host device; maintaining command latency information of multiple volatile memory types of the memory package;
6. The system of claim 1, wherein the host device includes a memory map of the storage device and latency information associated with each command of the commands.
sorting pending commands based on the command latency information; and
sorting pending commands according to a command latency associated with each of the volatile memory types of the multiple volatile memory types;
scheduling execution of the sorted pending commands by intermixing commands for a first type of volatile memory with commands for a second type of volatile memory to generate a command schedule,
determining a command schedule for a data interface between the host device and the memory package using commands for a first type of volatile memory and commands for a second type of volatile memory;
10. The method of claim 9, comprising: transmitting, from the host device to the memory package, a first command of the command schedule to access the first type of volatile memory, and executing the first command at the memory; transmitting, from the host device to the memory package, multiple second commands of the command schedule to access the second type of volatile memory; and executing the multiple second commands at the memory package during the latency of the first command.
wherein execution of a first command for the first type of volatile memory has greater latency than execution of multiple serially issued commands for the second type of volatile memory.
wherein a latency of a command for the first type of volatile memory is greater than a combined latency of multiple, serially-issued commands for the second type of volatile memory.
As shown above the first difference is that the instant claim specifies that the memory map includes the latency information. However, the US Patent has another claim, claim 6, that describes a memory map of the storage device and latency information. The second difference is that the instant claim specifies intermixing commands of the first type of memory and the second type. The US Patent has another claim, claim 10, that describes executing multiple second commands at the memory package during the latency of the first command, which is the result of intermixing. The combination of claims presented in the US Patent is therefore believed to obviously anticipate the instant claim.
Regarding claim 17 of the instant application, claims 1, 6, 7 and 9 of the US Patent are believed to obviously anticipate the claim language, similarly to what is presented above. The only difference is that the instant claim positively recites, “A host device comprising a processor configured to”. However, claim 1 of the US Patent describes, “a host device coupled to the storage device, the host device configured to issue commands to the storage device to store and retrieve information of the system.” A host device, as described in claim 1 of the US Patent would inherently include a processing element in order to issue commands and operate as claimed.
Claims 3 – 6, 8 – 11, 13 – 16, and 18 - 21 of the instant application are similarly obvious in view of claims 1 – 12, 14, and 17 – 18 of the US Patent.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 13 of U.S. Patent No. 11455098 in view of Farmahini Farahani et al. US Patent Application Publication No. 2019/0189210 (herein after referred to as Farmahini Farahani).
Regarding claim 7, the US Patent describes the method of claim 2 (see above). However, the US Patent does not specifically claim comprising servicing memory requests that match data in a cache portion of the storage device directly from the cache portion and without accessing the second type of volatile memory of the storage device.
Farmahini Farahani describes a hybrid memory module. Stacked volatile memory 512 is depicted in FIG. 5 as a 3-dimensional block including a first layer 577 and a second layer 578. In various embodiments, stacked volatile memory 512 may include more than two layers. In various embodiments, first layer 577 may include a cache controller 591 and a volatile memory 593. Volatile memory 593 may include both volatile memory data and volatile memory tags or only volatile memory data. Second layer 578 may include a volatile memory tag unit 592 and a data buffer 594. In various embodiments, volatile memory tag unit 592 is a segment of volatile memory used to store tags and/or is located any layer of stacked volatile memory 512 having the prescribed volatile memory. In various embodiments, cache controller 591, volatile memory tag unit 592, data buffer 594, and volatile memory 593 are on any of the prescribed layers. The number of layers in stacked volatile memory 512 may vary (e.g., increase or decrease) depending on, for example, system design requirements of hybrid memory module 521 (page 7, paragraph [0049]). During a read operation request sent by host 101 and received by cache controller 591, cache controller 591 generates a read command to read or access the contents of the volatile memory tags located in volatile memory tag unit 592 of stacked volatile memory 512. In response, volatile memory tag unit 592 provides tag data responses to cache controller 591. The tag data responses may contain, for example, the contents of tags and are provided to cache controller 591. Cache controller 591 assesses the tags to determine whether a tag is a hit or a miss in volatile memory 593 of stacked volatile memory 512. When a hit occurs, cache controller 591 becomes aware that data exists in volatile memory 593 and fetches or accesses the corresponding data from volatile memory 593. The data, if any, fetched from volatile memory 593 is provided to and buffered in a buffer portion of cache controller 591 (e.g., data buffer 594). When data is received by cache controller 591, cache controller 591 sends a command to host 101 to notify host 101 that data has been received by cache controller 591 and is ready for retrieval by host 101 (page 8, paragraph [0053]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Farmahini Farahani teachings in the US Patent ‘098 system. Skilled artisan would have been motivated to incorporate the method of including a cache layer as part of a stacked volatile memory as taught by Farmahini Farahani in the US Patent ‘098 system for effectively bringing the conventional benefits of caching, providing smaller faster memory in addition to larger slower memory, to a stacked volatile memory. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as stacked memory. This close relation between both of the references highly suggests an expectation of success.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 10 of U.S. Patent No. 12216906 in view of Farmahini Farahani et al. US Patent Application Publication No. 2019/0189210 (herein after referred to as Farmahini Farahani).
Regarding claim 7, the US Patent describes the method of claim 2 (see above). However, the US Patent does not specifically claim comprising servicing memory requests that match data in a cache portion of the storage device directly from the cache portion and without accessing the second type of volatile memory of the storage device.
Farmahini Farahani describes a hybrid memory module. Stacked volatile memory 512 is depicted in FIG. 5 as a 3-dimensional block including a first layer 577 and a second layer 578. In various embodiments, stacked volatile memory 512 may include more than two layers. In various embodiments, first layer 577 may include a cache controller 591 and a volatile memory 593. Volatile memory 593 may include both volatile memory data and volatile memory tags or only volatile memory data. Second layer 578 may include a volatile memory tag unit 592 and a data buffer 594. In various embodiments, volatile memory tag unit 592 is a segment of volatile memory used to store tags and/or is located any layer of stacked volatile memory 512 having the prescribed volatile memory. In various embodiments, cache controller 591, volatile memory tag unit 592, data buffer 594, and volatile memory 593 are on any of the prescribed layers. The number of layers in stacked volatile memory 512 may vary (e.g., increase or decrease) depending on, for example, system design requirements of hybrid memory module 521 (page 7, paragraph [0049]). During a read operation request sent by host 101 and received by cache controller 591, cache controller 591 generates a read command to read or access the contents of the volatile memory tags located in volatile memory tag unit 592 of stacked volatile memory 512. In response, volatile memory tag unit 592 provides tag data responses to cache controller 591. The tag data responses may contain, for example, the contents of tags and are provided to cache controller 591. Cache controller 591 assesses the tags to determine whether a tag is a hit or a miss in volatile memory 593 of stacked volatile memory 512. When a hit occurs, cache controller 591 becomes aware that data exists in volatile memory 593 and fetches or accesses the corresponding data from volatile memory 593. The data, if any, fetched from volatile memory 593 is provided to and buffered in a buffer portion of cache controller 591 (e.g., data buffer 594). When data is received by cache controller 591, cache controller 591 sends a command to host 101 to notify host 101 that data has been received by cache controller 591 and is ready for retrieval by host 101 (page 8, paragraph [0053]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Farmahini Farahani teachings in the US Patent ‘906 system. Skilled artisan would have been motivated to incorporate the method of including a cache layer as part of a stacked volatile memory as taught by Farmahini Farahani in the US Patent ‘906 system for effectively bringing the conventional benefits of caching, providing smaller faster memory in addition to larger slower memory, to a stacked volatile memory. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as stacked memory. This close relation between both of the references highly suggests an expectation of success.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter, in the event that the double patenting rejections above are overcome or addressed: Claim 2 describes, “a method comprising: maintaining a memory map of a storage device having multiple types of volatile memory, the memory map including command latency information for commands associated with each type of volatile memory of the multiple types of volatile memory; sorting pending commands based on the command latency information; and scheduling execution of the sorted pending commands by intermixing commands for a first type of volatile memory with commands for a second type of volatile memory to generate a command schedule, wherein execution of a first command for the first type of volatile memory has greater latency than execution of multiple serially issued commands for the second type of volatile memory.” Claims 9 and 17 include similar limitations. Claim 12 depends from claim 9 and therefore includes those same limitations. Daniels US Patent Application Publication No. 2008/0126716 describes that the hybrid memory controller 300 may re-order the commands based upon latencies associated with servicing the commands and priorities associated with the commands, to reduce latencies involved with accessing memory (page 4, paragraph [0042]). Furthermore, split logic 310 may separate the commands into a read command queue and a write command queue. In coming queue(s) 312 may have a second stage comprising one or more queues to maintain processed commands until arbiter 330 transmits the commands to DRAM queue(s) 340 or SRAM queue(s) 350 (page 4, paragraph [0044]). However, Daniels does not teach or suggest all of the limitations presented in the claims. King US Patent Application Publication No. 2015/0356048 describes activating the plurality of memory die in a timed and delayed sequence, wherein the activation of the plurality of memory die may cause the memory die to independently access the common bus for an activation period (page 2, paragraph [0019]). The enable signal may enable the delay 304, the code signal may program the delay 304 to provide an amount of delay associated with one of the plurality of memory die and further based on the type of command (page 4, paragraph [0029]). However, King does not teach or suggest all of the limitations presented in the claims. Rotithor et al. US Patent Application Publication No. 2005/0091460 describes a method for out of order memory scheduling intended to optimize latency. Read transactions are sorted into queues based upon selected attributes. For example, read transactions are sorted into queues based upon the read address and address mapping used by memory. Read transactions in each queue are sorted by arrival time. Other attributes including, but not limited to, CPU priority and demand vs prefetch transaction type may be used in sorting the transactions as well. Reads in separate queues will not have page conflicts with each other. A locally oldest transaction in each queue and globally oldest transaction among queues may be identified (page 3, paragraph [0038]). However, Rotithor does not teach or suggest all the limitations presented in the claims. Williams et al. US Patent No. 11150836 describes deterministic optimization via performance tracking in a data storage system. A scheduler circuit is configured to alter a first execution sequence of data access commands to the die set to a second execution sequence in response to a measured performance metric and determination that the first execution sequence is not optimal to guarantee the greatest possible read access latency consistency. However, Williams does not teach or suggest all of the limitations presented in the claims. Liu US Patent Application Publication No. 2020/0409846 describes that the prediction of DAR [data access request] execution latency allows the cache circuit 302 of the system module 290 to evaluate one or more hypothetical cache utilizations. For instance, the cache circuit 302 can evaluate one or more reorganizations of DARs between different caches 292/294/296 of the system module 290 to determine the optimal configuration of DARs to provide deterministic window performance to one or more hosts. Thus, the cache circuit 302 can develop a cache strategy from the results of the polling 298 and prediction 300 circuits that generates one or more proactive cache actions to increase the availability and accuracy of DAR execution consistency during a deterministic window (page 6, paragraph [0069]). It is contemplated that the cache 292/294/296 have different performance characteristics, such as capacity, data access speed, latency, and power consumption (page 5, paragraph [0066]). However, Liu does not teach or suggest all the limitations presented in the claims.
Conclusion
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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April 17, 2026
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