Prosecution Insights
Last updated: July 17, 2026
Application No. 19/030,129

SERVER AND DATA CENTER

Non-Final OA §103
Filed
Jan 17, 2025
Priority
Aug 24, 2022 — CN 202211019373.4 +1 more
Examiner
WILSON, ADRIAN S
Art Unit
Tech Center
Assignee
Xia Men Chuangpuyun Technology Co. Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
807 granted / 1112 resolved
+12.6% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
15 currently pending
Career history
1126
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
84.3%
+44.3% vs TC avg
§102
4.6%
-35.4% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1112 resolved cases

Office Action

§103
DETAILED ACTION Claims 1-12 have been considered for patentability. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 104932618 (CN 618) (from applicant’s IDS submitted on 12/18/2025) taken alone. In re Claim 1, CN 618 discloses a server, comprising: a chassis and a plurality of peripheral component interconnect express (PCIe) cards 302, wherein an internal space of the chassis comprises a first space (region occupied by power backplane 102 and power module 103; See Figures 1 and 4) and a second space (region occupied by GPU 101; See Figures 1 and 4) that are arranged in a height direction, the first space is located above the second space (Figure 1), the PCIe cards 302 are located in the second space, at least one interface of the PCIe card is facing the first space (Figures 1 and 4), the interface of the PCIe card is configured to connect to a power supply wire (paragraph 0041), the first space configured to accommodate the power supply wire (Figures 1 and 4, via motherboard 102) a height of the chassis is greater than or equal to 4U (paragraphs 0057, 0066). CN 618 does not explicitly disclose wherein the height of the second space is greater than or equal to 3 units. However, CN 618 does disclose a chassis having a TOTAL height of 4U (See above) within which a power module 103 and power backplane 102 are located in an upper space and the PCIe cards 302 are disposed in a lower space beneath them (Figures 1 and 4). Given this disclosed arrangement, the height of the second (i.e. lower) space is merely a result effective variable to that which is otherwise disclosed in CN 618. See MPEP §2144.05. Given that CN 618 discloses a 4U chassis, the lower space (i.e. second space) must be made large enough to accommodate the height of the PCIe cards 302 (industry standard heights of GPU being within 2U to 3U) while leaving sufficient clearance above (i.e. the first space) for the upward facing interface and power wire connections all while maintaining a 4U height. Optimizing this height to a value greater than or equal to 3U amounts to no more than routine optimization of a result effective variable and would have been an obvious modification to a person having ordinary skill in the art of modular electronics at a time before the effective filing date. In re Claim 2, CN 618 discloses wherein the interface 10111 of the PCIe card 1011 protrudes from an upper surface of the PCIe card and extends into the first space (See Figure 1). In re Claim 12, CN 618 discloses a GPU server “node” but does not explicitly disclose a plurality of servers. However, it has been held that it would have been an obvious modification to simply duplicate that which is otherwise disclosed in the prior art. MPEP §2144.04 (VI). CN 618 stated purpose is deploying “nodes” as basic units within a chassis of a larger data processing system, and thus strongly suggests a plurality of servers being that a “node” implies one of many. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 104932618 (CN 618) (from applicant’s IDS submitted on 12/18/2025) in view of Dent (US Patent 5,555,158). In re Claim 3, CN 618 discloses the limitations as noted above, but does not explicitly disclose wherein the server further comprises a mainboard, the mainboard is fastened to a bottom panel of the chassis, and the card is inserted into the mainboard. However, Dent discloses a mainboard 50, the mainboard is fastened to a bottom panel of a chassis (Figure 3), and a card is inserted into the mainboard (at 56). It would have been obvious to a person having ordinary skill in the art of modular electronics at a time before the effective filing date to have mounted the mainboard as otherwise disclosed in CN 618 to a bottom panel of a chassis as disclosed in Dent as a simple substitution of well known card mounting arrangements (direct insertion on a bottom fixed adapter board) to obtain predictable results of a shorter signal path and reduced part count. Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 104932618 (CN 618) (from applicant’s IDS submitted on 12/18/2025) in view of CN 109116937 (CN 937). In re Claims 4-6, CN 618 discloses the limitations as noted above, but does not explicitly disclose wherein there are at least 17 slots or 19 slots in a width direction of the second space, and the PCIe card occupies at least one of the at least 17 slots or 19 slots. However, CN 618 does disclose and suggests a wide GPU server chassis. CN 937 discloses double width GPU cards may be inserted into a mainboard PCIe slots and arranged side-by-side along the chassis width to maximize the number of GPUs. It would have been obvious to a person having ordinary skill in the art of modular electronics to have modified the number of slots to 17 given that CN 937 teaches maximizing side by side GPU density and the wide chassis (as disclosed in CN 618) may accommodate them. Providing at least 8 GPUs is only a mere duplication of parts beyond the 4 otherwise disclosed in CN 937. It has been held that a mere duplication of parts to that which is otherwise disclosed in the prior art is an obvious modification to a person of ordinary skill absent a showing of unpredictable results. See MPEP §2144.04 (VI). Claim(s) 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 104932618 (CN 618) (from applicant’s IDS submitted on 12/18/2025), Dent (US Patent 5,555,158) and further in view of Dao et al. (2017/0024347) (from applicant’s IDS submitted on 12/18/2025). In re Claim 7, CN 618 as modified by Dent discloses the limitations of Claim 3 above but does not explicitly disclose wherein the server further comprises a power supply unit, the internal space of the chassis further comprises a third space, the third space is parallel to the second space in a horizontal direction, and the power supply unit is located in the third space. However, Dao discloses a power supply unit 4, a third space of a chassis (region F, paragraph 0128), the third space parallel to a second space (side-by-side with I/O card regions), the power supply unit 4 in the third space. It would have been obvious to a person having ordinary skill in the art of modular electronics at a time before applicant’s effective filing date to have arranged a power supply unit in a third space, as disclosed in Dao, with the arrangement as otherwise disclosed and suggested in CN 618, to enable the laying of more modules in a limited space and maximize space utilization. Dao, paragraphs 0107, 0127, 0130. Relocating modules into lateral spaces beside a card region frees width for more modules/cards. In re Claim 8, Dao further discloses wherein the third space (region F) is located on a left side of a second space; or the second space comprises at least two subspaces, and the third space is located between two of the subspaces. See Dao, Figure 2. In re Claim 9, Dao further discloses wherein the server further comprises a first adapter board 2, there are a plurality of power supply units (Figure 2), and the plurality of power supply units are disposed side by side in the height direction of the chassis (Figure 2) and are connected to the mainboard (as disclosed in CN 618 as modified by Dent) through the first adapter board. In re Claim 10, Dao further discloses wherein the server further comprises an input/output interface 32 (3221, usb/vga/network), the internal space of the chassis further comprises a fourth space (region C), the fourth space is parallel to the second space in the horizontal direction (Figure 2), and the I/O interface is located in the fourth space. In re Claim 11, Dao further discloses wherein the server further comprises a second adapter board (two shared I/O units on the top and bottom plates of shared I/O housing 321; paragraph 0124), and there are a plurality of I/O interfaces; and the plurality of I/O interfaces are disposed side by side in the height direction of the chassis (Figure 2), and are connected to the mainboard (as disclosed in CN 618 as modified by Dent) through the second adapter board (interface 3221 connected through backplate 2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adrian S Wilson whose telephone number is (571)270-3907. The examiner can normally be reached Monday through Friday, 9am to 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L Parker can be reached at 303-297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADRIAN S WILSON/Primary Examiner, Art Unit 2841
Read full office action

Prosecution Timeline

Jan 17, 2025
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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EXPANSION MODULE, PCIE EXPANSION MODULE, CHASSIS ASSEMBLY, COMPUTER, AND SERVER CLUSTER
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
89%
With Interview (+16.3%)
2y 4m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1112 resolved cases by this examiner. Grant probability derived from career allowance rate.

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