DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 03/27/2026. Claims 1, 8, and 14 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.CN20240962755.3, filed on 07/18/2024.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2020/0019327), hereinafter Choi in view of Choi (US 2025/0053337), hereinafter Choi’337
Regarding claims 1, 8, and 14, taking claim 1 as exemplary, Choi teaches a method for collecting data based on data type, performed by a processing unit, comprising:
receiving a host write command carrying user data and a data type associated with the user data from a host side (Choi, [0011], In response to a write command provided along with a write logical address and write data; );
determining a specific data type from a plurality of data types comprising the data type carried in the host write command (Choi, [0125], classifies the data A, B, C, D, E, F, G and H stored in the specific pages SPG<BLOCK0_P22, BLOCK0_P34, BLOCK0_P43, BLOCK1_P44, BLOCK2_P12, BLOCK2_P31, BLOCK2_P41, BLOCK2_P42> as cold data);
determining a plurality of source blocks from a plurality of data blocks (Choi, [0125], the zeroth memory block BLOCK0 … the first memory block BLOCK1 … the second memory block BLOCK2);
collecting user data of valid physical pages of the specific data type from the source blocks (Choi, [0126], the controller 130 moves the cold data A, B, C, D, E, F, G and H stored in the eight specific pages SPG<BLOCK0_P22, BLOCK0_P34, BLOCK0_P43, BLOCK1_P44, BLOCK2_P12, BLOCK2_P31, BLOCK2_P41, BLOCK2_P42> to the third memory block BLOCK3 through a merge operation); and
programming collected user data of the valid physical pages of the specific data type into a destination block (Choi, [0126], the third memory block BLOCK3).
Choi does not explicitly teach host write command carrying … a data type associated with the user data from a host side, as claimed.
However, Choi in view of Choi’337 teaches receiving a host write command carrying user data and a data type associated with the user data from a host side (Choi’337, [0037], The host interface 121 provides an interface for communication with the host; [0125], receiving a write request for the cold data from the host 300; [0140], The host 300 may indicate that the data to be written is hot data or warm data through hint information included in a write command; Choi, [0011]);
determining a specific data type from a plurality of data types comprising the data type carried in the host write command (Choi’337, [0124], The controller 120 may recognize, through hint information included in a write request provided from the host 300, that the data to be written is cold data. The hint information indicates an attribute (e.g., hot/warm/cold) of the data requested to be written).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Choi to incorporate teachings of Choi’337 to receive a write command with hint information indicating the type of write data from a host and a memory controller determines a specific data type based on the hint information. A person of ordinary skill in the art would have been motivated to combine the teachings of Choi with Choi’337 because it improves efficiency and performance of the storage system disclosed in Choi by storing a specific data in a specific storage region based on the data type (Choi’337, [0008]).
Claims 8 and 14 have similar limitations as claim 1 and they are rejected for the similar reasons. Furthermore, regarding claim 14, Choi further teaches an apparatus for collecting data based on data type, comprising: a flash interface (I/F) (Choi, [0058], NAND flash interface), coupled to a flash module (Choi, [0058], When the memory device 150 is a flash memory or specifically a NAND flash memory … The NFC 142 may work as an interface (e.g., a NAND flash interface) for processing a command and data between the controller 130 and the memory device 150); and a processing unit (Choi, [0058], processor 134), coupled to the flash I/F (Choi, [0058], the NFC 142 may generate a control signal for the memory device 150 and process data to be provided to the memory device 150 under the control of the processor 134; Fig.1).
Claim(s) 2, 9, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Choi and Choi’337 as applied to claims 1, 8, and 14 respectively above, in view of Tai (US2018/0165010), hereinafter Tai, and further in view of Chang (US2016/0124844), hereinafter Chang.
Regarding claims 2, 9, and 15, taking claim 2 as exemplary, the combination of Choi teaches all the features with respect to claim 1 as outlined above. The combination of Choi does not explicitly teach the method of claim 1, comprising: sorting the data blocks in descending order according to valid page counts (VPCs) of the specific data type for the data blocks; and selecting a preset number of the data blocks starting from a data block with a largest VPC of the specific data type as the source blocks, as claimed.
However, the combination of Choi in view of Tai teaches the method of claim 1, comprising: sorting the data blocks in descending order according to valid page counts (VPCs) of the specific data type for the data blocks (Tai, [0023], In step S240, the iteration sorting circuit 114 of the controller 110 sorts all of the candidate blocks in the sorting set according to the metadata; [0024], According to the needs of the management operation, the sorting operation in step S240 may be incremental sorting or decremental sorting. For example … the metadata in step S240 are invalid data counts, and the sorting operation in step S240 may be decremental sorting).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Tai to sort a plurality of memory blocks in descending order according to number of valid pages. A person of ordinary skill in the art would have been motivated to combine the teachings the combination of Choi with Tai because it improves efficiency and performance of the storage system disclosed in the combination of Choi by allowing the storage system to quickly identify a candidate from a sorted list.
The combination of Choi does not explicitly teach selecting a preset number of the data blocks starting from a data block with a largest VPC of the specific data type as the source blocks, as claimed.
However, the combination of Choi in view of Chang teaches selecting a preset number of the data blocks starting from a data block with a largest VPC of the specific data type as the source blocks (Chang, [0028], the logical blocks corresponding to the run-time write block with the highest valid page count are all regarded as the selected logical blocks with the garbage collection performed thereon one by one to release the space of the run-time write block for reuse ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Chang to select memory blocks with the highest number of valid page count as victim blocks for garbage collection. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Chang because it improves performance of the storage system disclosed in the combination of Choi by performing a smaller number of random data writings.
Claims 9 and 15 have similar limitations as claim 2 and they are rejected for the similar reasons.
Claim(s) 3-4, 10-11, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Choi, Choi’337, Tai, and Chang as applied to claims 2, 9, and 15 respectively above, and further in view of Yang (US2022/0197862), hereinafter Yang and Kanno (US2017/0262228), hereinafter Kanno.
Regarding claims 3, 10, and 16, taking claim 3 as exemplary, the combination of Choi teaches all the features with respect to claim 2 as outlined above. The combination of Choi does not explicitly teach the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region of a designated physical page of each data block in a flash module, as claimed.
However, the combination of Choi in view of Yang teaches the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region (Yang, [0143], Regarding each memory block, the metadata can include … a valid page count (VPC); [0163], the memory system 110 may generate or update metadata used for the purpose of managing and controlling the memory device 150) of a designated physical page of each data block in a flash module.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Yang to include valid page count information as part of metadata for each memory block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Yang because it improves efficiency of the storage system disclosed in the combination of Choi by allowing the storage system to select memory blocks based on the number of valid pages.
The combination of Choi does not explicitly teach metadata region is a designated physical page of each data block in a flash module, as claimed.
However, the combination of Choi in view of Kanno teaches the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region (Yang, [0143]) of a designated physical page of each data block in a flash module (Kanno, [0406], management information, such as metadata, can be written to, for example, the last page of each block).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Kanno to store metadata such as valid page count for each memory block in the last page of each block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Kanno because it improves efficiency and performance of the storage system disclosed in the combination of Choi by providing a designated physical location for the storage system to retrieve metadata.
Claims 10 and 16 have similar limitations as claim 3 and they are rejected for the similar reasons.
Regarding claims 4, 11, and 17, taking claim 4 as exemplary, the combination of Choi teaches all the features with respect to claim 2 as outlined above. The combination of Choi does not explicitly teach the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region of a last physical page of each data block in a flash module, as claimed.
However, the combination of Choi in view of Yang teaches the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region (Yang, [0143], Regarding each memory block, the metadata can include … a valid page count (VPC); [0163], he memory system 110 may generate or update metadata used for the purpose of managing and controlling the memory device 150) of a last physical page of each data block in a flash module.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Yang to include valid page count information as part of metadata for each memory block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Yang because it improves efficiency of the storage system disclosed in the combination of Choi by allowing the storage system to select memory blocks based on the number of valid pages.
The combination of Choi does not explicitly teach metadata region is of a last physical page of each data block in a flash module, as claimed.
However, the combination of Choi in view of Kanno teaches the method of claim 2, comprising: reading a VPC of the specific data type from a metadata region (Yang, [0143]) of a last physical page of each data block in a flash module (Kanno, [0406], management information, such as metadata, can be written to, for example, the last page of each block).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Kanno to store metadata such as valid page count for each memory block in the last page of each block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Kanno because it improves efficiency and performance of the storage system disclosed in the combination of Choi by providing a designated physical location for the storage system to retrieve metadata.
Claims 11 and 17 have similar limitations as claim 4 and they are rejected for the similar reasons.
Claim(s) 5, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Choi, Choi’337, Tai, and Chang as applied to claims 2, 9, and 15 respectively above, and further in view of Yu (US2025/0278357), hereinafter Yu.
Regarding claims 5, 12, and 18, taking claim 5 as exemplary, the combination of Choi teaches all the features with respect to claim 2 as outlined above. The combination of Choi does not explicitly teach the method of claim 2, comprising: reading a VPC table from a designated physical address in a flash module; and obtaining the VPCs of the specific data type for all data blocks from the VPC table, as claimed.
However, the combination of Choi in view of Yu teaches the method of claim 2, comprising: reading a VPC table from a designated physical address in a flash module (Yu, [0081], The memory controller can send the mapping tables (including the L2P table, the VPC table and the checkpoint) to the memory device (e.g., non-volatile NAND memory) for storage; [0079]; [0080], The memory controller can update the VPC table by decreasing the valid page count of one or more blocks); and obtaining the VPCs of the specific data type for all data blocks from the VPC table (Yu, [0079], The VPC table records used logical addresses and the number of valid pages for each block in the memory device. The memory controller increases the number of valid pages (i.e., a valid page count) for a specific block by one, when the memory controller programs one page data into an empty page of the specific block and maps a logical address with the physical address of the empty page in the L2P mapping table).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Yu to include a valid page count table to store valid page count for each block in a flash module and store the valid page count table in the flash module. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Yu because it improves efficiency of the storage system disclosed in the combination of Choi by allowing the storage system to restore data using checkpoint in case of accidental power off (Yu, [0079]).
Claims 12 and 18 have similar limitations as claim 5 and they are rejected for the similar reasons.
Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Choi and Choi’337 as applied to claims 1 and 14 respectively above, and in view of Huang (US2023/0119688), hereinafter Huang.
Regarding claims 6 and 19, taking claim 6 as exemplary, the combination of Choi teaches all the features with respect to claim 1 as outlined above. The combination of Choi further teaches the method of claim 1, comprising: collecting a plurality of physical addresses of the valid physical pages of the specific data type in the source blocks according to a plurality of records of a plurality of host-address to flash- address mapping (H2F) sub-tables (Choi, [0006], managing mapping information for mapping logical addresses to physical addresses; classifying, as cold data, data stored in a specific page corresponding to the specific physical address among the pages; [0011], detect a first physical address mapped to the write logical address in the mapping information); and programming user data of the physical addresses into the destination block (Choi, [0126], the controller 130 moves the cold data A, B, C, D, E, F, G and H stored in the eight specific pages SPG<BLOCK0_P22, BLOCK0_P34, BLOCK0_P43, BLOCK1_P44, BLOCK2_P12, BLOCK2_P31, BLOCK2_P41, BLOCK2_P42> to the third memory block BLOCK3 through a merge operation).
In addition, Huang also teaches the method of claim 1, comprising: collecting a plurality of physical addresses of the valid physical pages of the specific data type in the source blocks according to a plurality of records of a plurality of host-address to flash- address mapping (H2F) sub-tables; and programming user data of the physical addresses into the destination block (Huang, [0069], the SSD may need to maintain an address mapping table for translating the logical page address (LPA) of a storage request into a physical page address (PPA) … the garbage collector may first select the candidate flash blocks … migrate the valid pages of the selected blocks to a free block).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Huang to obtain physical page addresses of valid pages for cold data in one or more memory blocks from a logical to physical address mapping and move the data of the valid pages to a destination memory block. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Huang because it improves efficiency of the storage system disclosed in the combination of Choi by allowing the storage system to move valid data from used memory blocks in order to erase and reuse the used memory blocks.
Claim 19 has similar limitations as claim 6 and is rejected for the similar reasons.
Claim(s) 7, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Choi, Choi’337, and Huang as applied to claims 6 and 19 respectively above, and further in view of Cariello (US2024/0045799), hereinafter Cariello and Cho et al. (US2010/0115190), hereinafter Cho.
Regarding claims 7 and 20, taking claim 7 as exemplary, the combination of Choi teaches all the features with respect to claim 6 as outlined above. The combination of Choi does not explicitly teach the method of claim 6, wherein most-significant n bits of each record of each H2F sub-table stores information of data type, and remaining bits of each record of each H2F sub-table stores a physical address, where n is set to any integer from 1 to 5, as claimed.
However, the combination of Choi in view of Cariello teaches the method of claim 6, wherein most-significant n bits of each record of each H2F sub-table stores information of data type, and remaining bits of each record of each H2F sub-table stores a physical address, where n is set to any integer from 1 to 5 (Cariello, [0062], the L2P change record 360 may include an L2P record 365 that includes a physical address field 350 (e.g., a pointer) and a flag 355 (e.g., a stream identification field) that indicates the type of the data associated with the logical address; [0064], the L2P change records 360 may include a portion (e.g., one or more bits) of a data type indication; Fig.3B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified combination of Choi to incorporate teachings of Cariello to include a data type field in a logical-to-physical address mapping table. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Cariello because it improves efficiency of the storage system disclosed in the combination of Choi by allowing the storage system to identify entries of a specific data type based on a flag value.
Cariello teaches storing a data type indicator using least-most-significant n bits of a L2P record, nevertheless, Cariello does not teach wherein most-significant n bits of each record of each H2F sub-table stores information of data type, as claimed.
However, the combination of Choi in view of Cho teaches wherein most-significant n bits of each record of each H2F sub-table stores information of data type (Cho, [0031], the FTL uses a block level translation scheme, and each entry represents an address of a physical block mapping to a logical block, and the most significant bit is used as the flag; Cariello, [0062], the L2P change record 360 may include … a flag 355 … that indicates the type of the data associated with the logical address).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Choi to incorporate teachings of Cho to have most-significant n bits (MSB) of each address translation entry to store a flag value, such as type of data (in L2P records of Cariello). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Choi with Cho because it improves efficiency and flexibility of the storage system disclosed in the combination of Choi by allowing the storage system to use a MSB flag as a separator for each record without adding extra spaces when L2P records are stored in a log structure.
Claim 20 has similar limitations as claim 7 and is rejected for the similar reasons.
Regarding claim 13, the claim is rejected for the same reasons set forth with respect to claims 6 and 7, as claim 13 recites limitations that are similar to those recited in claims 6 and 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US2018/0254092) teaches a valid page count table storing valid page count for each of the blocks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137
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