Prosecution Insights
Last updated: October 25, 2026
Application No. 19/030,193

SYSTEMS AND METHODS FOR CONFIGURATION OF SEQUENCE HANDLERS

Final Rejection §DOUBLEPATENT
Filed
Jan 17, 2025
Priority
Sep 08, 2021 — provisional 63/241,592 +2 more
Examiner
YIMER, GETENTE A
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Sandpiper Cdn LLC
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
549 granted / 622 resolved
+33.3% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
9 currently pending
Career history
632
Total Applications
across all art units

Statute-Specific Performance

§101
8.4%
-31.6% vs TC avg
§103
84.4%
+44.4% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§DOUBLEPATENT
Detailed Action Response to Amendment Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are presented for examination. Claims 1-2,10-11 and 19 are amended. Claims 3-9,12-18 and 20 are originally presented. Claims 1-20 are rejected. This Action is Final. Response to Arguments Applicant's arguments filed 07/08/2026 have been fully considered but they are not persuasive. Double Patenting The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). 8. Claim 1 is non-provisionally rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,265,491. Application No: 19/030,193 Patent No: 12,265,491 1. A method for registering a handler in a configured sequence of handlers, the method comprising: receiving, by a processor and memory storing instructions implementing a sequencer infrastructure, a configuration script defining a sequence comprising one or more handler identifiers and corresponding one or more handler arguments; invoking, by the processor, a handler initialization entry point for a handler corresponding to a handler identifier of the one or more handler identifiers, the invoking the handler initialization entry point comprising: selecting, based on the corresponding one or more handler arguments, a handler type, and initializing a configured handler based on the handler type selected and the corresponding one or more handler arguments; adding, by the processor, the configured handler to a configured sequence of handlers; and executing, by a sequencer of the sequencer infrastructure, the configured sequence of handlers to generate an output in response to an input. 1. A method for registering a handler, by a processor, in a configured sequence of handlers, the method comprising: receiving, by the processor and memory storing instructions implementing a sequencer infrastructure, a configuration script defining a sequence comprising one or more handler identifiers and corresponding one or more handler arguments; invoking, by the processor, a handler initialization entry point for a handler corresponding to a handler identifier of the one or more handler identifiers, the invoking the handler initialization entry point comprising: selecting, by the processor and based on the corresponding one or more handler arguments, a handler type, and initializing, by the processor, a configured handler based on the handler type selected and the corresponding one or more handler arguments; adding, by the processor, the configured handler to a configured sequence of handlers; and executing, by a sequencer of the sequencer infrastructure, the configured sequence of handlers to generate an output in response to an input. 9. Claims 1- 20 are non-provisionally rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,265,491 (Please note that as both the Patent and co-pending application claimed similar subject matters, and in the interest of time, the examiner is selecting the independent claim 1 from the Patent and claim 1 from co-pending application for the instant double patenting rejection). Allowable Subject Matter 10. Claims 1-20 are would be allowable by filing a Terminal Disclaimer to overcome the non-statutory obviousness-type double patenting rejection as being unpatentable over claim 1 of U.S. Patent No. 12,265,491. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). References Considered Pertinent but not relied upon CLEMENT et al. (US Patent Application Pub. No: 20240104001 A1 ) teaches a debugging tool identifies the smallest subset of an input sequence or rationales that influenced a neural language model to generate an output sequence. CLEMENT discloses the debugging tool uses the rationales to understand why the model made its predictions and in particular, the particular input tokens that had the most impact on the output sequence. CLEMENT suggests in the case of erroneous output, the rationales are used to alter the input sequence to avoid the error or to tailor a new training dataset to retrain the model to improve its performance. Damani et al. (US Patent Application Pub. No: 20230144553 A1) teaches a computing system including one or more processor and one or more memory that stores application code that configures the processor to execute an application. Damani discloses the system includes logic to identify high and low register utilization regions of the application code and insert register acquire instructions and register release instructions in the application code by the compiler, such that when executed by the processor, the application code borrows and returns registers to an inter-block register pool when execution enters a high and low register utilization region, respectively. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached on Monday-Friday 6:30-3:00.Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair my.uspto.gov/pair/ PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GETENTE A YIMER/Primary Examiner, Art Unit 2181
Read full office action

Prosecution Timeline

Jan 17, 2025
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §DOUBLEPATENT
Jul 08, 2026
Response Filed
Oct 01, 2026
Final Rejection mailed — §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+8.2%)
2y 5m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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