DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 11,934,332. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims only remove limitations from the issued patent claims. The pending claim claims “circuitry to” while the patented claim claims “a data shuffle unit”. The patented claim claims a network device while the pending claim only claims located remotely. The pending claims also remove the limitations from the parent that was added to made them allowable.
Pending claim 21 reads:
A system, comprising: a device located remotely from a data source and a data target, wherein the device comprises circuitry to: receive data from the data source; receive a descriptor that describes a data shuffle operation to perform on the data; perform the data shuffle operation on the data to produce shuffled data; and provide the shuffled data to the data target.
Patent claim 1 reads:
A network device, comprising: a device interface that receives data from at least one data source; and a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target, wherein the descriptor comprises at least one of a work queue element (WQE) posted to a queue pair, a memory region description, a description of a Remote Direct Memory Access (RDMA) request, and a description of an application-level request.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-22, 24, 26, 29, 31, 38-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers et al PN 5,961,640 in view of Bonn PN 6,597,661.
In regards to claim 21, 31, 39: Chambers et al teaches a system, comprising: a device (figure 3B) from a data source (device in domain 1) and a data target (device in domain 2), wherein the device comprises circuitry to: receive data (interface 200a) from the data source (device in domain 1); receive a descriptor (descriptor in packet header Abstract “Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet.”) that describes a data shuffle operation to perform on the data big endian to little endian or little endian to big endian or no conversion figure 5 Column 10 lines 26 et. seq. "At step 525, control circuit 270 reads bit 0 of ENDIAN.sub.- ALIGN [1:0] field 368 to determine if it is of value zero (little endian format). If so, then step 530 is entered as the input is in little endian format. If not, then step 540 is entered as the input is in big endian format. At step 530, control circuit 270 reads bit 1 of ENDIAN.sub. ALIGN [1:0] field 368 to determine if it is of value zero (little endian format). If so, then "A" is entered (FIG. 7A) as the input is in little endian format and the output is little endian format and no conversion is required. If not, then "B" (FIG. 7B) is entered as the input is in little endian format but the output is in big endian format and endian conversion is required. Processes "A" and "B" both return to step 550”); perform the data shuffle operation on the data to produce shuffled data (converted from big to little or little to big endian); and provide the shuffled data to the data target (device in domain 2). Chambers et al only talks about the data from/to the interfaces (210 and 226) without indicating if the data source/target is directly connected or remotely connected to the interfaces 210/226. Bonn expressly teaches remote targets and sources in a “network” (Column 3 lines 38-60 "Networked computer systems that use byte ordering schemes other than Big Endian generally have functions for converting between Big Endian network standard byte order and their internal order, called "host order." For example, on a computer system using Little Endian byte ordering, the Unix function ntohl() converts the value on line (1) in Big Endian network standard byte order to the representation on line (3) in Little Endian host order"). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use Chambers et al' endian conversion in between networked device as exemplified in Bonn because different endianness is known in network devices.
In regards to claim 22: Chambers et al teaches the conversion being based upon descriptors from the source (included in the header of a packet from the source).
In regards to claim 24: Chambers et al teaches the descriptor is an instruction descriptor.
In regards to claim 26: Chambers et al teaches the descriptor us from a memory region (“FIFO memory unit per read cycle; and a control circuit for reading an endian alignment descriptor of the input packet indicating a first endian format of the first bus and a second endian format of the second bus, the control circuit responsive to the endian alignment descriptor for performing endian conversion during read cycles of the plurality of FIFO memory units”).
In regards to claims 29, 38: Chambers et al teaches the endianness is part of a communication scheme between devices and is hidden/transparent.
In regards to claim 30: Chambers teaches the endianness swapping is performed in a read or write. “the control circuit responsive to the endian alignment descriptor for performing endian conversion during read cycles of the plurality of FIFO memory units by controlling the read pointer register and the signal bus to access and supply bytes from the plurality of FIFO memory units in predetermined orders”.
Claim(s) 23, 34-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers et al PN 5,961,640 in view of Bonn PN 6,597,661 as applied to claim 21 above, and further in view of Boucher et al PN 2002/0156927.
In regards to claim 23: Chambers teaches the endianness being stored in a descriptor in a header but the endianness is from the host. Boucher et al teaches an intelligent NIC INIC that runs FreeBSD and ([0341] “We choose to violate this because much of the FreeBSD code modifies the packet headers as it examines them (mostly for endian conversion purposes)”). It would have been obvious to allow intelligent NIC’s to determine endianness and modify the header to determine endianness. Because this would have removed the job of determining endianness from the source/target.
In regards to claims 34: Chambers et at leaches the descriptors is obtained from the source, and the descriptors are used to perform multiple shuffle operations. Bonn teaches a network device can be the source. Chambers also teaches the target can be a memory.
In regards to claim 35-36: Chambers et al teaches the descriptor is in a packet. Bonn teaches a network device may be a source/target.
Claim(s) 32, 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers et al PN 5,961,640 in view of Bonn PN 6,597,661 as applied to claim 21 above, and further in view of MA et al PN 2014/0082120.
In regards to claim 32: Chambers et al teaches conversion between Domains but does not specify the domains are peer to peer memories. Ma et al teaches endian conversion Para [0025] between peer memories Para [0007,0011,0024]. It would have been obvious to a person of ordinary skill in the art to allow endian conversion between peer memories because this would have prevented limiting the devices in the system.
In regards to claim 40: Ma teaches image/graphics data.
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers et al PN 5,961,640 in view of Bonn PN 6,597,661 as applied to claim 21 above, and further in view of Johnson et al PN 5,317,715.
In regards to claim 37: Chambers et al teaches data type conversion from big endian to little endian and vice versa. Johnson teaches endianness conversion (figures 5A,5B) included in data packing “The invention features a reduction in the amount of hardware required to connect peripherals on the Remote Bus to the Local Bus. Additional features of the invention include the flexibility to perform bus sizing, data packing and unpacking, and conversions between byte and half-word data packed into words”). It would have been obvious to include data packing because this would have allowed dynamic bus sizing.
Allowable Subject Matter
Claims 25, 27, 28, 33 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and addressing the double patenting.
Claims 25, 27, 28, 33 returns the limitation that was included in the parent patent to make it allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/Paul R. MYERS/ Primary Examiner, Art Unit 2176
Prosecution Insights