DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 7-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
The double patenting rejection is withdrawn in view of the approved terminal disclaimer.
The §112 rejections are withdrawn in view of the amendment to claim 9.
Regarding the §103 rejections, Applicant first argues that the reference voltage in Shigehisa is not “predetermined” as recited in the amended claims. Examiner disagrees. A predetermined parameter is simply one that is designated in advance. It does not need to have a pre-set value to be predetermined. In this case, predetermined voltage reads on a voltage that is designated in advance to be used as the “ground” voltage in the physical configuration of the circuit and in the calculations implemented by the processor. Shigehisa teaches the designation of a given terminal, labeled GND and connected via line G2, to serve as the zero reference voltage for the circuit, i.e. ground. That predetermined voltage is generated at terminal GND for use in the circuit and in calculations, thereby meeting the limitation.
Applicant also argues that Shigehisa does not teach generating the ground voltage in the distal end portion. However, the claims do not require the voltage generation circuit to be in a distal end. Structurally, it is only required that the camera unit comprises a reference voltage generation circuit that generates the voltage. A reasonably broad construction of the recited “camera unit” includes the overall camera system, including both the distal end portion and the body. Thus, Shigehisa’s generation of the ground voltage at the body, i.e. supplying a zero-reference voltage at the GND terminal, meets the limitation.
Next, Applicant argues that Shigehisa fails to meet the recited conversion circuit for converting the second power source voltage (i.e. the measured operating voltage) into a signal that indicates the second power source voltage. Examiner maintains that the reference meets the limitation.
First, in computing, to convert a voltage from one signal to another can mean mere re-labelling, e.g. storing the same voltage value in a different data field or assigning the value of one variable as the new value of a second variable. In this sense, Shigehisa converts the operating voltage V1d into a signal voltage V1s that indicates the current operating voltage for purposes of controlling the power supply. V1d itself is not used directly to control the power supply—it is first converted (at least logically) to V1s. The signals V1d and V1s are not the same value. Although Amp1 is designed to mitigate it, some voltage drop will occur across line Fb and thus convert the value of V1d into a different value, V1s.
Applicant also suggests that the conversion must happen in the distal end portion of Shigehisa to meet the limitation. But as discussed above, the claims do not require that the conversion circuit be in the distal end specifically, only that it resides in the “camera unit” which includes the overall imaging system and is not limited to only the distal end or only the camera lens, etc.
Lastly, Applicant argues that to modify Shigehisa with the teaching of Adachi would destroy the principle of operation of Shigehisa. Examiner does not agree that the mere removal of Shigehisa’s feedback line would impair or significantly hinder the principle of operation of Shigehisa. The feedback signal that Shigehisa uses to determine the first (and indirectly, the second) command signal would still be sent, it would simply be time-multiplexed onto a single carrier. The logical processing would not be affected. The motivation to combine is to obviate the necessity of a separate communication line so that the device can be made more compact with fewer components.
For the reasons above, the rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shigehisa et al., US 2018/0199003 in view of Adachi, US 2016/0213238.
Claims 1 and 5. Shigehisa teaches a camera unit and method, comprising:
an image sensor configured to receive a first power source voltage [power supply P supplies V1, Fig. 1, paras. 18, 22-24, 57, 70] transferred by a power source line [L1, Fig. 1] as a second power source voltage [distal end portion voltage V1D, Fig. 1, para. 59, 71-77] and generate a video signal by using the second power source voltage [image pickup 21, Fig. 1, paras. 18-23, 32];
a reference voltage generation circuit configured to generate a first reference voltage [ground is a reference voltage that designates zero volts; other voltages are relative (referenced) to ground; ground is based on GND in distal portion, Fig. 1, para. 26];
a conversion circuit configured to convert the second power source voltage so as to generate a voltage signal having a first voltage indicating the second power source voltage [V1d is converted to V1s by line Fb, Fig. 1, paras. 61, 64]; and
signal output circuit configured to output the video signal [paras. 22-24], a reference signal having the first reference voltage [GND on line G2, Fig. 1, para. 26], and the voltage signal [V1s is output on line Fb, Fig. 1, 39, 61, 64].
Shigehisa is silent on outputting different signals on one line, i.e. multiplexing the signals. Adachi teaches a signal output circuit configured to output a video signal [imaging signal output, Fig. 2, paras. 51, 52] and a reference signal having the first reference voltage [reference signal, based on a reference voltage, is transmitted in different period from same output (e.g. reading unit 24), Fig. 2, paras. 51, 52, 113; note imaging signal has a frame rate, para. 108, 127, 128] to a video signal line [signals are time-multiplexed for output, paras. 51, 52].
Before the effective filing date of the claimed invention, it would have been obvious to one skilled in the art to transmit the recited signals via a single line by time-division multiplexing them as taught in Adachi, to minimize the wiring needed to pass from the distal end to the apparatus body. This saves space in the insertion portion, allowing for small size and saving room for other components.
3. Shigehisa teaches the output of a video signal [paras. 22-24], a reference signal having the first reference voltage [GND on line G2, Fig. 1, para. 26], and the voltage signal [V1s is output on line Fb, Fig. 1, 39, 61, 64].
Adachi teaches outputting different signals in different respective time periods as recited [paras. 51, 52].
4. Adachi teaches an endoscope of which a distal end is to be inserted into a living body, the endoscope comprising the camera unit according to claim 1, wherein the camera unit is disposed in the distal end [Figs. 1, 2, paras. 24-29].
6. Shigehisa teaches a camera unit and method, comprising:
an image sensor configured to receive a first power source voltage [power supply P supplies V1, Fig. 1, paras. 18, 22-24, 57, 70] transferred by a power source line [L1, Fig. 1] as a second power source voltage [distal end portion voltage V1D, Fig. 1, para. 59, 71-77] and generate a video signal by using the second power source voltage [image pickup 21, Fig. 1, paras. 18-23, 32];
a reference voltage generation circuit configured to generate a first reference voltage [ground is a reference voltage that designates zero volts; other voltages are relative (referenced) to ground; ground is based on GND in distal portion, Fig. 1, para. 26];
a conversion circuit configured to convert the second power source voltage so as to generate a voltage signal having a first voltage indicating the second power source voltage [V1d is converted to V1s by line Fb, Fig. 1, paras. 61, 64]; and
signal output circuit configured to output the video signal [paras. 22-24], a reference signal having the first reference voltage [GND on line G2, Fig. 1, para. 26], and the voltage signal [V1s is output on line Fb, Fig. 1, 39, 61, 64].
a control unit including:
a signal reception circuit configured to receive the video signal [receiving section 41, Fig. 1, paras. 24, 28], the reference signal [GND in apparatus body 2, Fig. 1, para. 25] and the voltage signal [control section C receives feedback voltage, Fig. 1, paras. 44, 61];
a calculation circuit configured to calculate a control value used for adjusting a value of the first power source voltage by using the reference signal and the voltage signal [power supply control section C calculates a driving voltage value based on V1s and ground reference, Figs. 1-3, paras. 25, 36, 37, 49, 55];
a power source voltage generation circuit configured to generate the first power source voltage and output the generated first power source voltage to the power source line [power supply P, Figs. 1-3, paras. 55, 56, 63, 64]; and
a voltage adjustment circuit configured to adjust the value of the first power source voltage by controlling the power source voltage generation circuit based on the control value [voltage adjustment sections, Figs. 2, 3, paras. 48, 58, 59, 74].
Shigehisa is silent on outputting different signals on one line, i.e. multiplexing the signals. Adachi teaches a signal output circuit configured to output a video signal [imaging signal output, Fig. 2, paras. 51, 52] and a reference signal having the first reference voltage [reference signal, based on a reference voltage, is transmitted in different period from same output (e.g. reading unit 24), Fig. 2, paras. 51, 52, 113; note imaging signal has a frame rate, para. 108, 127, 128].
Before the effective filing date of the claimed invention, it would have been obvious to one skilled in the art to transmit the recited signals via a single line by time-division multiplexing them as taught in Adachi, to minimize the wiring needed to pass from the distal end to the apparatus body. This saves space in the insertion portion, allowing for small size and saving room for other components.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shigehisa and Adachi as cited above, further in view of Minakuchi, US 2015/0280550.
2. The above references are silent on converting (adjusting) the second voltage (the voltage applied at the image sensor) to a specified range. Minakuchi teaches a voltage control system for an endoscope wherein a value of the second power source voltage [VL, Fig. 2] is not within a range of a voltage of the video signal, wherein the conversion circuit is configured to convert the second power source voltage into the first voltage having a value within the range so as to generate the voltage signal [when VL is outside the rated voltage, VL is adjusted to be within specified voltage range by adjusting P1/V1 so that VL is within range, Figs. 1, 2, paras. 14, 16, 38-40, 45, 46, 54, 59, 64].
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the references, maintaining an applied voltage within the specified range of the imager, preventing damage to the imager and ensuring proper operation and usable image signals.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy R Newlin whose telephone number is (571)270-3015. The examiner can normally be reached M-F 8-5 Mountain Time.
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/TIMOTHY R NEWLIN/Examiner, Art Unit 2424
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