DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on Jan. 25, 2024. It is noted, however, that applicant has not filed a certified copy of the 13103010 application as required by 37 CFR 1.55.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: ELECTROPHORESIS DISPLAY HAVING GATE DRIVING CIRCUIT ENABLE LINES.
Claim Objections
Claims 8 and 10 are objected to because of the following informalities:
Claim 8 recites “the enabling control nodes” of claim 1, whereas claim 1 recites “enable control nodes”.
Claim 10 recites “the output equivalent capacitance value” of claim 2, whereas claim 2 is silent regarding the “value”. It appears that it may be “an output equivalent capacitance value” of “the output equivalent capacitor”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 8-10, 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2015/0179109 A1) in view of Zhou et al. (US 2006/0139305 A1).
As to claim 1, Hsu teaches an electrophoretic display (Hsu, FIG. 3, [0020], “electrophoretic display 300”), comprising:
a substrate (Hsu, FIG. 3, [0020], a substrate comprising “electrophoretic panel 302, timing control circuit 304, data driving circuit 306, gate driving circuit 308 and gate line enabling circuit 310”, etc.) having a first surface and a second surface (Hsu, FIG. 3, [0020], it is inherent that the substrate must have a back surface and a front surface);
a pixel control array (Hsu, FIG. 3, [0020], “electrophoretic panel 302”) arranged on the second surface (Hsu, FIG. 3, [0020], it is inherent the “electrophoretic panel 302” must be arranged on the front surface); and
a gate control circuit (Hsu, FIG. 3, [0020], “gate driving circuit 308” in association with “gate line enabling module GLEi”) electrically connected to (Hsu, see FIG. 3, [0020], via “N first gate lines F1-Fn” and “N second gate lines S1-Sn”) the pixel control array (Hsu, FIG. 3, [0020], “electrophoretic panel 302”);
wherein the pixel control array (Hsu, FIG. 3, [0020], “electrophoretic panel 302”) comprises:
a plurality of pixel units (Hsu, FIG. 3, [0020], “a plurality of pixels”), at least one of the pixel units comprising a pixel thin film transistor (Hsu, FIGS. 4A-4C, [0021], “thin-film transistors”);
a plurality of gate lines (Hsu, see FIG. 3, [0020], “N first gate lines F1-Fn” and “N second gate lines S1-Sn”), at least one of the gate lines (Hsu, see FIG. 3, [0020], “N second gate lines S1-Sn”) connected to gates of the pixel thin film transistors (Hsu, see FIGS. 3-4, [0021], “switch SWi”) of the plurality of pixel units (Hsu, FIGS. 3-4, [0020], the “plurality of pixels”);
a plurality of data lines (Hsu, FIG. 3, [0020], “data lines D1-Dm”), at least one of the data lines (Hsu, FIG. 3, [0020], “data lines D1-Dm”) connected to sources or drains of the pixel thin film transistors (Hsu, see FIGS. 3-4, “switch SWi”) of the plurality of pixel units (Hsu, FIGS. 3-4, [0020], the “plurality of pixels”); and
wherein the gate control circuit (Hsu, FIG. 3, [0020], “gate driving circuit 308” in association with “gate line enabling module GLEi”) comprises:
a plurality of gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”), one of the gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], each of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”) comprising a plurality of gate driving circuits (Hsu, e.g., FIG. 4A, [0021], “FTFTi” and “STFTi”), one of the gate driving circuits (Hsu, e.g., FIG. 4A, [0021], “STFTi”) comprising a gate thin film transistor (Hsu, e.g., see FIG. 4A, [0021], “STFTi” receiving “gate low voltage VGL”), wherein at least one of the gate thin film transistors is low conduction resistive thin film transistor (Hsu, e.g., see FIG. 4A, [0021], “STFTi” receiving “gate low voltage VGL”; low conduction resistive thin film transistor is substantially the same as conventional TFT), an output terminal of the gate driving circuit (Hsu, e.g., see FIG. 4A, [0021], output terminal of “STFTi” receiving “gate low voltage VGL”) connected to the gate line (Hsu, e.g., see FIG. 4A, [0021], “second gate line Si”) of the pixel control array (Hsu, FIG. 3, [0020], “electrophoretic panel 302”);
a plurality of control signal lines (Hsu, FIGS. 3-4, [0021], “first gate line Fi”), one of the control signal lines (Hsu, FIGS. 3-4, [0021], “first gate line Fi”) connected to an input end of one of the gate driving circuits (Hsu, e.g., FIG. 4A, [0021], “FTFTi”) of the gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”);
a plurality of gate driving circuit set enable lines (Hsu, FIGS. 3-4, [0021], “output enable signal OEi”) connected to enable control nodes of the gate driving circuits (Hsu, e.g., FIG. 4A, [0021], the gate of “FTFTi”) of the gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”).
Hsu does not explicitly teach “a storage capacitor and a pixel electrode”.
However, Zhou teaches the concepts of a storage capacitor (Zhou, FIG. 5, [0063], “capacitor 23”) and a pixel electrode (Kim, FIGS. 4-5, [0060], “counter electrode 6”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “pixels” taught by Hsu to further comprise the “capacitor 23” and “counter electrode 6”, as taught by Zhou, in order to maintain pixel state and reduce flicker in bistable media.
As to claim 4, Hsu teaches the electrophoretic display in claim 2, wherein an output terminal of the gate driving circuit (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”) is source or drain of the gate thin film transistor (Hsu, e.g., see FIG. 4A, [0021], drain of “STFTi” receiving “gate low voltage VGL”).
As to claim 8, Hsu teaches the electrophoretic display in claim 1, wherein the enabling control node of the gate driving circuit (Hsu, e.g., FIG. 4A, [0021], the gate of “FTFTi”) is gate of a thin film transistor with low conduction resistance (Hsu, e.g., FIG. 4A, [0021], the gate of “FTFTi”).
As to claim 9, Hsu teaches the electrophoretic display in claim 1, wherein one of the gate driving circuits (Hsu, e.g., FIG. 4A, [0021], “FTFTi” and “STFTi”) comprises a front-stage thin film transistor (Hsu, e.g., FIG. 4A, [0021], “FTFTi”) and a rear-stage thin film transistor (Hsu, e.g., FIG. 4A, [0021], “STFTi”) with low conduction resistance, and the enable control node of the gate driving circuit (Hsu, e.g., FIG. 4A, [0021], the gate of “FTFTi”) is a gate of the front-stage thin film transistor (Hsu, e.g., FIG. 4A, [0021], “FTFTi”).
As to claim 10, Hsu in view of Kim does not explicitly teach the electrophoretic display in claim 2, wherein the output equivalent capacitance value is provided by a capacitor formed by sandwiching an insulating layer between two conductive layers in a thin film transistor process.
However, Kim teaches the concept that the storage capacitance value (Kim, FIG. 3, e.g., the value of “Cst”) is provided by a capacitor (Kim, FIG. 3, “Cst”) formed by sandwiching an insulating layer (Kim, FIG. 3, [0058], e.g., “insulating layer 10 covering the control electrode GE and storage line STL”) between two conductive layers (Kim, FIG. 3, [0058], e.g., between “storage line STL” and “pixel electrode PE”) in a thin film transistor process (Kim, see FIG. 3).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to form the “output capacitor CC_o” taught by Kim as in FIG. 3, as taught by Kim, in order to provide “CC_o” and “Cst” together in the same thin film transistor process.
As to claim 12, Hsu in view of Kim does not explicitly teach the electrophoretic display in claim 1, wherein the substrate is a glass substrate or a flexible polymer material substrate.
However, Examiner takes an Official Notice that it is old and well known in the art of electrophoretic display that the substrate is a glass substrate or a flexible polymer material substrate.
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to configure the substrate for the “electrophoretic display 300” taught by Hsu to be “a glass substrate or a flexible polymer material substrate”, as a mere engineering choice.
As to claim 13, Hsu in view of Zhou teaches the electrophoretic display in claim 1, wherein output terminals of the plurality of gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”) output three types of states including high voltage level and low voltage level (Hsu, e.g., see FIGS. 4D-4F, “VGH” and “VGL”) and high output impedance (Zhou, FIGS. 3A-8B, [0046], “IUP1 or IUP2”). Examiner renders the same motivation as in claim 1.
As to claim 14, Hsu in view of Zhou teaches the electrophoretic display in claim 1, wherein at least one output of the gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”) is of high impedance at least once during image update period (Zhou, FIGS. 3A-8B, [0046], “IUP1 or IUP2”). Examiner renders the same motivation as in claim 1.
As to claim 17, Hsu in view of Zhou teaches the electrophoretic display in claim 1, wherein at least one output of the gate driving circuit sets (Hsu, FIGS. 3-4, [0020]-[0021], pairs of “gate driving circuit 308” and corresponding “gate line enabling module GLEi”) is a high voltage level (Hsu, e.g., see FIGS. 4D-4F, “VGH”) at least once during image update period (Zhou, FIGS. 3A-8B, [0046], “IUP1 or IUP2”). Examiner renders the same motivation as in claim 1.
Claims 11 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2015/0179109 A1) in view of Zhou et al. (US 2006/0139305 A1) and Wang et al. (US 2013/0187149 A1).
As to claim 11, Hsu in view of Zhou does not explicitly teach the electrophoretic display in claim 1, wherein the pixel thin film transistors and the gate thin film transistors are amorphous silicon thin film transistors, organic thin film transistors, or indium gallium zinc oxide (IGZO) thin film transistors.
However, Wang teaches the concept that the pixel thin film transistors and the gate thin film transistors are amorphous silicon thin film transistors, organic thin film transistors, or indium gallium zinc oxide (IGZO) thin film transistors (Wang, FIG. 2, [0027], “TFT 200a depicted in FIG. 2A may be used in … electrophoretic display devices”; [0029], “semiconductor layer 260 comprises IGZO”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to configure the pixel TFT and gate TFT to be “TFT 200a” comprising “IGZO layer 260”, as taught by Wang, in order to “resolve the deterioration of the TFT and the decrease in mobility” (Wang, [0026]).
As to claim 7, Hsu in view of Zhou and Wang does not explicitly teach the electrophoretic display in claim 1, wherein a channel width/channel length (W/L) ratio of one of the gate thin film transistors is greater than 50/1.
However, Wang teaches the “channel width/channel length(W/L) ratio of TFT 200a” except that the value is greater than 50/1.
At the time of effective filing date, especially when there is no support describing why such specific adjusting value is made, it would have been obvious to one having ordinary skill in the art to adjust the ratio as an engineering choice, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954).
Allowable Subject Matter
Claims 2-3, 5-6, 15-16 and 18-23 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the closest known prior art, i.e., Hsu et al. (US 2015/0179109 A1), Zhou et al. (US 2006/0139305 A1), Wang et al. (US 2013/0187149 A1), Van Veenendaal et al. (US 2012/0092319 A1), He et al. (US 2018/0090088 A1) and Kim et al. (US 2016/0322015 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “one of the gate driving circuits comprises an output equivalent capacitor”.
As to claim 3, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “a capacitance value of the output equivalent capacitor is not less than 1pF”.
As to claim 5, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the low conduction resistance is no more than 1M Ohm”.
As to claim 6, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “the low conduction resistance is no more than 100K ohm”.
As to claim 15, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “output of 50% of the gate driving circuit sets are of high impedance at least once during image update period”.
As to claim 16, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “output of 50% of the gate driving circuit sets are low voltage level at least once during the image update period”.
As to claim 18, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “outputs of all gates of the gate driving circuit sets are low voltage level at least once during image update period”.
As to claims 19-23, they directly or indirectly depend from claim 2, and are allowable at least for the same reason above.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Van Veenendaal et al. (US 20120092319 A1) teaches the concept of “common electrode driver 570” (FIG. 5A); and He et al. (US 2018/0090088 A1) teaches the concept of “gate line gating control module 12” (e.g., FIG. 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Feb. 2, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2621
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