Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
1. The terminal disclaimer filed on 6/17/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 6/17/2026 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Willey et al. (Pub. No. US2014/0115208)
As per claim 1, Willey discloses a system comprising:
a memory device (fig.1, system memory 110);
a memory controller (fig.1, controller hub 115) coupled to the memory device; and
logic configured to perform operations (fig. 1, switch 120 referred as a logical assembly of multiple devices) comprising: selecting one virtual channel of multiple virtual channels to return credits to (paragraph 95, map to a single Channel value for crediting) based on determining that the one virtual channel has the most credits to return among the multiple virtual channels(paragraph 33, Credit-based flow control can be used to realize virtual channels and networks utilizing the interconnect fabric);
setting a credit return field of a first flow control unit (flit) for the selected virtual channel (paragraph 70-74, The flit headers include a Virtual network Adaptive (VNA) field. In one example, when a VNA field is set to a first value, the field can indicate that the flit is using VNA credits.)); and
contemporaneously sending multiple flits including the first flit and the second flit (paragraph 45, lines 8-, HPI splits the headers into corresponding slots to enable multiple messages in the flit destined for different nodes.)
As per claims 8 and 14, Willey discloses a method comprising:
selecting one virtual channel of multiple virtual channels to return credits to (paragraph 95, map to a single Channel value for crediting); based on determining that the one virtual channel has the most credits to return among the multiple virtual channels (paragraph 33, Credit-based flow control can be used to realize virtual channels and networks utilizing the interconnect fabric);
setting a credit return field of a first flow control unit (flit) for the selected virtual channel (paragraphs 70-74, the flit headers include a Virtual network Adaptive (VNA) field. In one example, when a VNA field is set to a first value, the field can indicate that the flit is using VNA credits.); and
contemporaneously sending multiple flits including the first flit and a second flit (paragraph 45, lines 8-, HPI splits the headers into corresponding slots to enable multiple messages in the flit destined for different nodes.)
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As per claims 2, 9 and 18, Willey discloses wherein the operations further comprise: setting values of one or more fields of the first flit to identify a first virtual channel, a first number of credits, a second virtual channel, and a second number of credits (paragraph 70, the Link layer can utilize multiple different types of virtual network or virtual channel credits. In one example, pooled virtual network adaptive (VNA) credits can be supported and a VNA field can be provided, the VNA field indicates a non-VNA flit (e.g., a flit that utilizes a different credit pool))
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As per claims 3, 10 and 16, Willey discloses wherein: the one or more fields of the first flit comprise a 1-bit first field and a 1-bit second field(paragraph 90, HPI can provide that every header flit includes single bit fields serving as a mechanism for bulk credit returns or bulk acknowledges); and
the setting of the values of the one or more fields of the first flit comprises: setting a value of the 1-bit first field of the first flit to indicate whether the first number of credits is for the first virtual channel or a third virtual channel (paragraph 90, lines 3-5, setting such fields to a "1" can indicates a refund of 8 VNA credits (in the case of the CRD field) or 8 ACKs (in the case of the ACK field); and
setting a value of the 1-bit second field of the first flit to indicate whether the second number of credits is for the second virtual channel or a fourth virtual channel (paragraphs 70-74, the Link layer utilize multiple different types of virtual network or virtual channel credits. The Link layer can use the Message Class field as part of the virtual channel (VC) definition. The flit headers include a Virtual network Adaptive (VNA) field. In one example, when a VNA field is set to a first value, the field can indicate that the flit is using VNA credits.)
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As per claims 4, 11 and 17, Willey discloses wherein the memory controller comprises a memory controller chiplet (fig. 1, within a memory controller hub (MCH) 115).
As per claims 5 and 18, Willey discloses wherein the sending of the multiple flits comprises sending the multiple flits from a chiplet (paragraph 45, lines 8-, HPI splits the headers into corresponding slots to enable multiple messages in the flit destined for different nodes.)
As per claims 6, 12, 19, Willey discloses wherein the selected virtual channel is dedicated to priority read requests (paragraph 85, control flits can be identified and handled differently than other flits so that the flit takes priority).
As per claims 7, 13 and 20, Willey discloses wherein the selected virtual channel is dedicated to read responses (paragraph 34, Transactions to the configuration space can include read requests and write requests).
4. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Safranek et al. [Pub. No. US2014/0112339] discloses the HPI Coherence Protocol can utilizes four of the virtual channels: REQ, WB, SNP, and RSP. The virtual channels can be used to unwind dependency cycles and avoid deadlock.
Response to Amendment
5. Applicant's amendment filed on 6/21/2026 have been fully considered but does not place the application in condition for allowance.
a. Applicant argues that Willey does not explicitly disclose a single channel value for crediting. Examiner respectfully disagrees. Willey notes at paragraph 33, Examiner further cites for clarification, Credit-based flow control can be used to realize virtual channels and networks utilizing the interconnect fabric, count the number of credits consumed by each TLP. The Link Layer can also be responsible for virtualizing the physical channel into multiple virtual channels and message classes. The Protocol layer 520a, b relies on the Link layer 510a, b to map protocol messages into the appropriate message classes and virtual channels before handing them to the Physical layer 505a,b for transfer across the physical links as further cited in paragraph 46, this is equivalent as Applicant’s recites claims. Thus, the prior art teaches the invention as claimed and the amended claims do not distinguish over the prior art as applied.
Applicant' s arguments are thus not persuasive towards patentability of the claims as presented and the rejections of record are maintained.
Conclusion
6. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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