DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the instant application.
Claim Objections
Claims 12 and 16-19 are objected to because of the following informalities:
Claim 12, lines 3-4, recite “the dummy line”. To keep consistency in the claim language, examiner suggest “the at least one dummy line”.
Claims 16-19 depend directly or indirectly from claim 12, therefore are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “wherein the at least one anode comprises a blue-pixel anode”. However, claim 10 depends on claim 7 which depends on claim 5 and claim 5 recites “wherein the at least one anode comprises a green-pixel anode”. It is unclear on how the at least one anode is both a green pixel anode and a blue-pixel anode.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 13-14 and 19 of U.S. Patent No. 12,223,891 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations are fully addressed (located within) the claims of issued Patent 12,223,891 B2. This is an anticipatory obviousness type double patenting rejection.
Current Application 19031266
U.S. Patent No. 12,223,891 B2
Claim 1. A display substrate, which comprises a display region having at least one data signal line and at least one anode, and
a bonding region located on one side of the display region;
wherein the display region at least comprises a first wiring region and a second wiring region;
the first wiring region comprises at least one first wiring;
the second wiring region comprises at least one second wiring;
the at least one first wiring and the at least one second wiring are connected to the at least one data signal line, a first terminal of the at least one first wiring is connected with a bonding lead line of the bonding region, a second terminal of the at least one first wiring is connected with a first terminal of the at least one second wiring after extending along a second direction, and a second terminal of the at least one second wiring is connected with the at least one data signal line after extending along a first direction; and
in the first wiring region, an orthographic projection of the at least one first wiring in a plane of the display substrate at least partially overlaps an orthographic projection of the at least one anode in the plane of the display substrate.
Claim 2. The display substrate according to claim 1, wherein the at least one first wiring and the at least one second wiring are arranged at a same layer.
Claim 20. A display apparatus, comprising the display substrate according to claim 1.
Claim 1. A display substrate, which comprises a display region and
a bonding region located on one side of the display region,
the display region at least comprising a first wiring region and a second wiring region,
wherein the first wiring region is provided with at least one first wiring and at least one light emitting device,
the second wiring region is provided with at least one second wiring and at least one light emitting device, and
the at least one light emitting device in the first region and the at least one light emitting device in the second region both comprise an anode;
a first terminal of the at least one first wiring is connected with a bonding lead line of the bonding region, a second terminal of the at least one first wiring is connected with a first terminal of the at least one second wiring after extending along a second direction, and a second terminal of the at least one second wiring is connected with data signal line of the display region after extending along a first direction, wherein the first direction crosses the second direction; and
the first wiring region further comprises at least one first compensation line extending along the first direction, an orthographic projection of at least one anode in a plane of the display substrate overlaps at least partially with an orthographic projection of the at least one first compensation line in the plane of the display substrate, and/or, the second wiring region further comprises at least one second compensation line extending along the second direction, and an orthographic projection of at least one anode in the plane of the display substrate overlaps at least partially with an orthographic projection of the at least one second compensation line in the plane of the display substrate.
Claim 2. The display substrate according to claim 1, wherein an orthographic projection of at least one anode in the plane of the display substrate at least partially overlaps an orthographic projection of the at least one first wiring in the plane of the display substrate.
Claim 13. The display substrate according to claim 1, wherein in a plane perpendicular to the display substrate, the display substrate comprises a drive circuit layer disposed on a substrate and an emitting structure layer disposed on one side of the drive circuit layer away from the substrate; the drive circuit layer comprises a plurality of conductive layers, and the data signal line is disposed in different conductive layers from the at least one first wiring and the at least one second wiring, and the at least one second wiring is connected to the data signal line through a via hole.
Claim 14. The display substrate according to claim 13, wherein the at least one first wiring, the at least one second wiring, the at least one first compensation line, and the at least one second compensation line are arranged on a same layer.
Claim 19. A display apparatus, comprising the display substrate according to claim 1.
Claims 3-4 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,223,891 B2 in view of Wang et al. (US 20220358879 A1, hereinafter referenced as Wang).
Regarding Claim 3, claims 1-2 of U.S. Patent No. 12,223,891 B2 teaches the display substrate according to claim 1.
The claims of U.S. Patent No. 12,223,891 B2 do not explicitly disclose wherein the display substrate comprises a pixel drive circuit in which active layers of at least two transistors are of different materials.
However, Wang teaches wherein the display substrate comprises a pixel drive circuit in which active layers of at least two transistors are of different materials (see Fig. 2A, para. [0050], para. [0052], para. [0063]. FIG. 2A is a schematic view of an equivalent circuit of a pixel circuit of a single pixel. The driving transistor T1, the switch transistor T2, the initializing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, and the anode reset transistor T7 all are P type transistors with polysilicon active layers. The compensating transistor T3 and the leakage preventing transistor T8 are both N type transistors with metal oxide active layers).
U.S. Patent No. 12,223,891 B2 and Wang are related to display devices thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display substrate disclosed by the claims of U.S. Patent No. 12,223,891 B2 With Wang’s teachings, since when the pixel circuit includes polysilicon transistors and metal oxide transistors, a working power consumption of the pixel circuit will be easily to reduce (Wang para. [0050]). In addition, the transistors with metal oxide active layers possess a leakage less character when turned off. When the driving transistor T1 drives the organic light emitting diode OLED to emit light, the leakage preventing transistor T8 is turned off to suppress an electrical potential at the control end of the driving transistor T1 from fluctuating and then to prevent from a large leakage current at the control end do the driving transistor T1 which causes issues at low frequency display of the organic light emitting diode. When the driving transistor T1 drives the organic light emitting diode OLED to emit light, the compensating transistor T3 is turned off. The compensating transistor T3 possess a leakage less character when turned off to suppress the leakage current collected at output end of the driving transistor T1 through the anode reset transistor T7 from leaking through the compensating transistor T3 to improve the issue of uneven brightness by the anode shunted when the organic light emitting diode OLED displays the low gray scale (Wang para. [0063]).
Regarding Claim 4, claims 1-2 of U.S. Patent No. 12,223,891 B2 teaches the display substrate according to claim 1.
The claims of U.S. Patent No. 12,223,891 B2 do not explicitly disclose wherein the at least two transistors comprise a low temperature polysilicon transistor and a metal oxide transistor.
However, Wang teaches wherein the at least two transistors comprise a low temperature polysilicon transistor and a metal oxide transistor (see Fig. 2A, para. [0050], para. [0052], para. [0063]. Transistors with polysilicon active layers in the disclosure all are low temperature polysilicon transistors. FIG. 2A is a schematic view of an equivalent circuit of a pixel circuit of a single pixel. The driving transistor T1, the switch transistor T2, the initializing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, and the anode reset transistor T7 all are P type transistors with polysilicon active layers. The compensating transistor T3 and the leakage preventing transistor T8 are both N type transistors with metal oxide active layers).
U.S. Patent No. 12,223,891 B2 and Wang are related to display devices thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display substrate disclosed by the claims of U.S. Patent No. 12,223,891 B2 With Wang’s teachings, since when the pixel circuit includes polysilicon transistors and metal oxide transistors, a working power consumption of the pixel circuit will be easily to reduce (Wang para. [0050]). In addition, the transistors with metal oxide active layers possess a leakage less character when turned off. When the driving transistor T1 drives the organic light emitting diode OLED to emit light, the leakage preventing transistor T8 is turned off to suppress an electrical potential at the control end of the driving transistor T1 from fluctuating and then to prevent from a large leakage current at the control end do the driving transistor T1 which causes issues at low frequency display of the organic light emitting diode. When the driving transistor T1 drives the organic light emitting diode OLED to emit light, the compensating transistor T3 is turned off. The compensating transistor T3 possess a leakage less character when turned off to suppress the leakage current collected at output end of the driving transistor T1 through the anode reset transistor T7 from leaking through the compensating transistor T3 to improve the issue of uneven brightness by the anode shunted when the organic light emitting diode OLED displays the low gray scale (Wang para. [0063]).
Regarding Claim 14, claims 1-2 of U.S. Patent No. 12,223,891 B2 teaches the display substrate according to claim 1.
The claims of U.S. Patent No. 12,223,891 B2 do not explicitly disclose wherein the pixel drive circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a first node, and a first electrode of the third transistor is connected with the fourth transistor through the first node.
However, Wang teaches wherein the pixel drive circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a first node, and a first electrode of the third transistor is connected with the fourth transistor through the first node (see annotated Fig. 5 bellow, para. [0054]-[0055]. As depicted in annotated Fig. 5 below, the pixel circuit comprises a first transistor (T4), a second transistor (T3), a third transistor (T1), a fourth transistor (T2), and a first node (N1), and a first electrode of the third transistor (T1) is connected with the fourth transistor (T2) through the first node (N1)).
PNG
media_image1.png
572
554
media_image1.png
Greyscale
U.S. Patent No. 12,223,891 B2 and Wang are related to display devices thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display substrate disclosed by the claims of U.S. Patent No. 12,223,891 B2 With Wang’s pixel circuit, since it would have provided a pixel circuit that improves the issue of uneven brightness (Wang para. [0060], para. [0063]).
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,223,891 B2 in view of Xuan et al. (US 20210193022 A1, hereinafter referenced as Xuan).
Regarding Claim 13, claims 1-2 of U.S. Patent No. 12,223,891 B2 teaches the display substrate according to claim 1.
The claims of U.S. Patent No. 12,223,891 B2 do not explicitly disclose wherein the pixel drive circuit comprises eight transistors and one storage capacitor, and the eight transistors comprise a low temperature polysilicon transistor.
However, Xuan teaches wherein the pixel drive circuit comprises eight transistors and one storage capacitor, and the eight transistors comprise a low temperature polysilicon transistor (see Fig. 11, para. [0110]. The first transistor M1 to the eighth transistor M8 may all be N-type thin film transistors or P-type thin film transistors, the process can be unified to be beneficial for improving the yield of products. Considering that a leakage current of a low-temperature polysilicon thin film transistor is small, in an exemplary embodiment, all transistors are low-temperature polysilicon thin film transistors, and thin film transistors with bottom gate structures or thin film transistors with top gate structures may be selected as long as switch functions can be realized)
U.S. Patent No. 12,223,891 B2 and Xuan are related to display devices thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display substrate disclosed by the claims of U.S. Patent No. 12,223,891 B2 with Xuan’s pixel circuit, since by providing a pixel circuit with all the transistors to be a low temperature polysilicon transistors the process can be unified to be beneficial for improving the yield of products (Xuan para. [0110]). In addition, leakage current of a low-temperature polysilicon thin film transistor is small (Xuan, para. [0110]).
Allowable Subject Matter
Claims 5-9, 11, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12 and 16-19 would be allowable if rewritten to overcome the objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IVELISSE MARTINEZ QUILES whose telephone number is (571)270-7618. The examiner can normally be reached Monday thru Friday; 1:00 PM to 5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached at 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IM/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 12/31/25