DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 6/24/2026. Claims 1 and 3-11 are pending and are under examination. The previous Non-Final rejection dated on 3/24/2206 has been withdrawn in view of a new ground of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 8-11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Willard (US 2022/0190826).
Regarding claim 1, Willard’s figures 3 and 8 shows A radio frequency (RF) switch circuit, comprising a plurality of stages of switch transistor units connected in series (T1 to Tn), wherein the switch transistor unit in each stage comprises a switch transistor (T1 to Tn), a gate bias resistor (Rg1 to Rgn), a bulk bias resistor (Rb1 to Rbn), a path resistor (Rds1 to Rdsn), a mirror resistor (802; figure 8A), and a dynamic adjustment unit (each pairs of BCb cascaded together in figure 8A), wherein a gate of each switch transistor (T1 to Tn) is connected to the corresponding gate bias resistor (Rg1 to Rgn), a drain and a source of each switch transistor are respectively connected to the corresponding path resistors (Rds1 to Rdsn), and a bulk of each switch transistor is connected to the corresponding bulk bias resistor (803; figure 8A); after the gate bias resistors in the stages of switch transistor units are connected in series to each other in sequence, a last gate bias resistor (Rg1)is connected to a gate bias voltage (Vg); after the bulk bias resistors in the stages of switch transistor units are connected in series to each other in sequence, a last bulk bias resistor (Rb1) is connected to the bulk bias voltage (Vb); the mirror resistors (802; figure 8A) are connected in series to each other in sequence to form a mirror resistor chain; and the bulk of each switch transistor is connected to an intermediate terminal (a node where two of BCb connected in series at node A; figure 8A) of the corresponding dynamic adjustment unit (pair of BCb; figure 8A), and a first side terminal (c node of one of the pair BCb; figure 8A) and a second side terminal (the other c node of the other pair of BCb; figure 8A) of the dynamic adjustment unit are respectively and wherein the dynamic adjustment unit (each pair of BCb; figure 8A) comprises an even number of identical diodes (figure 9B shows BCb comprises of two identical diodes); half of the diodes are connected in series to form a first diode sequence, and a negative terminal of the first diode sequence is connected to the first side terminal; the other half of the diodes are connected in series to form a second diode sequence, and a negative terminal of the second diode sequence is connected to the second side terminal; and a positive terminal of the first diode sequence and a positive terminal of the second diode sequence are connected to each other and then connected to the intermediate terminal as called for in claim 1.
Regarding claim 3, Willard’s figures 3 and 8 shows A radio frequency (RF) switch circuit, comprising a plurality of stages of switch transistor units connected in series (T1 to Tn), wherein the switch transistor unit in each stage comprises a switch transistor (T1 to Tn), a gate bias resistor (Rg1 to Rgn), a bulk bias resistor (Rb1 to Rbn), a path resistor (Rds1 to Rdsn), a mirror resistor (802; figure 8A), and a dynamic adjustment unit (each pairs of BCb cascaded together in figure 8A), wherein a gate of each switch transistor (T1 to Tn) is connected to the corresponding gate bias resistor (Rg1 to Rgn), a drain and a source of each switch transistor are respectively connected to the corresponding path resistors (Rds1 to Rdsn), and a bulk of each switch transistor is connected to the corresponding bulk bias resistor (803; figure 8A); after the gate bias resistors in the stages of switch transistor units are connected in series to each other in sequence, a last gate bias resistor (Rg1)is connected to a gate bias voltage (Vg); after the bulk bias resistors in the stages of switch transistor units are connected in series to each other in sequence, a last bulk bias resistor (Rb1) is connected to the bulk bias voltage (Vb); the mirror resistors (802; figure 8A) are connected in series to each other in sequence to form a mirror resistor chain; and the bulk of each switch transistor is connected to an intermediate terminal (a node where two of BCb connected in series at node A; figure 8A) of the corresponding dynamic adjustment unit (pair of BCb; figure 8A), and a first side terminal (c node of one of the pair BCb; figure 8A) and a second side terminal (the other c node of the other pair of BCb; figure 8A) of the dynamic adjustment unit are respectively the dynamic adjustment unit comprises an even number of identical switch transistors (figure 9B); drains and sources of half of the switch transistors are connected in series to form a first switch transistor sequence, and a source of the first switch transistor sequence is connected to the first side terminal; drains and sources of the other half of the switch transistors are connected in series to form a second switch transistor sequence, and a source of the second switch transistor sequence is connected to the second side terminal; and a drain of the first switch transistor sequence and a drain of the second switch transistor sequence are connected to each other and then connected to the intermediate terminal as called for in claim 3.
Regarding claim 4, wherein the gate and the drain of each switch transistor are directly connected, to form a diode connection (figure 9B).
Regarding claim 5, wherein in the dynamic adjustment unit, when a voltage difference between the first side terminal and the second side terminal is less than a first predetermined voltage value, a voltage of the intermediate terminal is not affected by a voltage of the first side terminal and a voltage of the second side terminal; and when the voltage difference between the first side terminal and the second side terminal is greater than a second predetermined voltage value, the voltage of the intermediate terminal is adjusted to be close to a smaller one of the voltage of the first side terminal and the voltage of the second side terminal (figure 9b).
Regarding claim 6, wherein each of the mirror resistors and the corresponding path resistor satisfy the following proportional relationship: Rci=kxRdsi, wherein i is a positive integer and 1 <i< n, Rei is a resistance value of a mirror resistor in an ith-stage switch transistor unit, Rdsiis a resistance value of a path resistor in the ith-stage switch transistor unit, and k is a proportionality coefficient (figure 8A).
Regarding claim 8, wherein in the plurality of stages of switch transistor units (T1 to Tn) connected in series, a source of the switch transistor in a current stage is connected to a drain of the switch transistor in a next stage.
Regarding claims 9-10, Willard’s RF switch circuit can be formed by an integrated circuit chip of an electronic device.
Regarding claim 11, wherein in the dynamic adjustment unit, when a voltage difference between the first side terminal and the second side terminal is less than a first predetermined voltage value, a voltage of the intermediate terminal is not affected by a voltage of the first side terminal and a voltage of the second side terminal; and when the voltage difference between the first side terminal and the second side terminal is greater than a second predetermined voltage value, the voltage of the intermediate terminal is adjusted to be close to a smaller one of the voltage of the first side terminal and the voltage of the second side terminal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Willard (US 2022/0190826) in view of applicant’s admitted prior art figure 1.
Regarding claim 7, Willard reference discloses a RF switch circuit comprising all the aspects of the present invention as noted above except for the gate of each switch transistor is connected to one end of the corresponding gate bias resistor, another end of the gate bias resistor is directly connected to the gate bias voltage, the bulk of each switch transistor is connected to one end of the corresponding bulk bias resistor, and another end of the bulk bias resistor is directly connected to the bulk bias voltage as called for in claim 7.
Applicant’s admitted prior art figure 1 shows a RF switch circuit comprising the gate of each switch transistor is connected to one end of the corresponding gate bias resistor (Rg), another end of the gate bias resistor is directly connected to the gate bias voltage (Vg), the bulk of each switch transistor is connected to one end of the corresponding bulk bias resistor (Rb), and another end of the bulk bias resistor is directly connected to the bulk bias voltage (Vb). Such an arrangement is to ensure the RF circuit capable of withstanding high voltage with a fast switching speed. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to rearrange Willard’s gate bias resistors and bulk bias resistors as taught by Applicant’s admitted prior art for the purpose of withstanding high voltage with a fast switching speed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Genc (USP 11,671,090) discloses a methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 8/13/2026
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