DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7, 9-10, 12-13, 15-16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basso (US 20240086070 A1), in view of Huang (US 20260026398 A1)
Regarding Claim 1, Basso teaches:
A method comprising: detecting a read error associated with data obtained (Basso, [0011] In some instances, a memory system may detect one or more errors when reading data from a first page (e.g., a first virtual page) of a block of memory cells.) based on a request from a host device(Basso, Fig. 3, 305);
identifying a data frame, of a virtual block, that stores the data; (Basso, abstract, In some instances, data may be read from a first page of a virtual block of a memory system)
performing scan operations or host read operations on the virtual block; (Basso, abstract, In some instances, data may be read from a first page of a virtual block of a memory system)
determining whether the read error is localized to less than a portion of the virtual block, based on performing the scan operations or the host read operations; (Basso, [035] The memory system 110 (e.g., the memory system controller 115) may continue reading data from adjacent pages 175 until no errors are detected (or until a quantity of errors below a threshold value is detected) and may refresh the pages 175 including errors. Accordingly, the memory system 110 may refresh only those pages 175 needing to be refreshed, as opposed to refreshing the entire block 170 of memory cells, which may improve the overall latency of the memory system 110.)
Basso teaches:
(Basso, [035] Accordingly, the memory system 110 may refresh only those pages 175 needing to be refreshed, as opposed to refreshing the entire block 170 of memory cells, which may improve the overall latency of the memory system 110.)
But does not explicitly teach:
and performing a data refresh of a data stripe of the virtual block based on determining whether the read error is localized to less than the portion of the virtual block,
However, Huang teaches:
(Huang, [0036] The memory sub-system controller 115 can be responsible for other memory management operations, such as wear leveling operations, garbage collection operations, error detection and ECC operations, encryption operations, caching operations, media scans (where different block stripes are read and analyzed for errors to determine whether to refresh or fold the block stripe))
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine virtual block and selective refreshing from Basso with dynamic stripe refreshing as taught by Huang, because dynamic data-refresh scan reads all data and identifies the error status of all blocks as a background operation. If a certain threshold of errors per block or ECC unit is exceeded in this scan, a refresh operation is triggered. (Huang, [0012])
Basso in view of Huang further teaches:
wherein the data stripe includes the data, (Basso, abstract, In some instances, data may be read from a first page of a virtual block of a memory system.) (Huang, [0036] where different block stripes are read and analyzed for errors)
and wherein the data refresh is performed without performing a data refresh of other data stripes of the virtual block. (Basso, [035] Accordingly, the memory system 110 may refresh only those pages 175 needing to be refreshed, as opposed to refreshing the entire block 170 of memory cells, which may improve the overall latency of the memory system 110.) (Huang, [0036] media scans (where different block stripes are read and analyzed for errors to determine whether to refresh or fold the block stripe))(Examiner’s note: both Basso and Huang show selective refreshing which will only affect the affected page/stripe)
Regarding Claim 2, Basso in view of Huang teaches:
The method of claim 1, comprising: including the virtual block in a pool of virtual blocks that are monitored; (Basso, Fig. 3, 320, [0062] In some instances, the blocks 325 may represent one or more physical blocks of memory cells. A virtual block may refer to a group of one or more blocks 325 (e.g., a group of one or more physical blocks) within which concurrent operations may occur. For example, concurrent operations may be performed on one or more of blocks 325-a through 325-m, and such blocks may collectively be referred to as a virtual block. As described herein, the block 325-a may be associated with a virtual block.)
and performing the scan operations or the host read operations on the virtual blocks included in the pool of virtual blocks. (Basso, [0063] The memory system controller 315 may perform various operations associated with the memory system 310. For example, the memory system controller 315 may receive commands (e.g., read commands, write commands) from the host system 305, and read and write data corresponding to memory cells of the pages 330 and the pages 335 of the blocks 325 in response to receiving the commands, among other operations)
Regarding Claim 4, Basso in view of Huang teaches:
The method of claim 1, comprising: determining that the read error is localized to less than the portion of the virtual block; (Basso, [035] Accordingly, the memory system 110 may refresh only those pages 175 needing to be refreshed, as opposed to refreshing the entire block 170 of memory cells, which may improve the overall latency of the memory system 110.)
and performing the data refresh of the data stripe of the virtual block based on determining that the read error is localized to less than the portion of the virtual block. (Basso, [035] Accordingly, the memory system 110 may refresh only those pages 175 needing to be refreshed, as opposed to refreshing the entire block 170 of memory cells, which may improve the overall latency of the memory system 110.)
Regarding Claim 5, Basso in view of Huang teaches:
The method of claim 1, comprising: determining that the read error is not localized to less than the portion of the virtual block; (Basso, [0033] In some cases, a memory system controller 115 or a local controller 135 may perform operations (e.g., as part of one or more media management algorithms) for a memory device 130, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof...To avoid waiting for all of the pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170. )
and performing a complete data refresh of the virtual block based on determining that the read error is not localized to less than the portion of the virtual block. (Basso, [0031] such copying and remapping may be performed instead of erasing and rewriting the entire old block 170 due to latency or wearout considerations [0033] To avoid waiting for all of the pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170. Examiner's note: This implies that refreshing the whole block when it's full of invalid data is a conventional method)
Regarding Claim 7, Basso in view of Huang teaches:
The method of claim 1, comprising: determining a number of the scan operations or the host read operations based on a storage device that includes the virtual block; (Basso, [0070] Additionally or alternatively, the memory system controller 315 may compare a quantity of access operations performed on a page 330 to a first threshold Thx (e.g., an access threshold))
and determining the number of the scan operations or the host read operations based on a workload associated with the storage device. (Basso, [0070] By way of example, Thx may be set to five million (5,000,000) reads and the memory system controller 315 may determine a quantity of access operations performed on the first page 330-d. That is, the memory system controller 315 or other circuitry included in the memory system 310 may include a counter configured to track a quantity of access operations performed on each block 325, each page 330, or both. I)
Regarding Claims 9-10 and 12-13,
The system of claims 9-10 and 12-13 performs the same method steps as the method of claims 1-2 and 4-5, and claims 9-10 and 12-13 are therefore rejected using the same rationale set forth above in the rejection of claims 1-2 and 4-5
Basso in view of Huang further teaches:
controller (Basso, Fig. 1, 115)
Regarding Claims 15-16 and 18-19,
The medium of claims 15-16 and 18-19 performs the same method steps as the method of claims 1-2 and 4-5, and claims 15-16 and 18-19 are therefore rejected using the same rationale set forth above in the rejection of claims 1-2 and 4-5
Basso in view of Huang further teaches:
non-transitory computer-readable medium (Basso, [0034] The system 100 may include any quantity of non-transitory computer readable media that support read disturb management for memory. )
Claim(s) 6, 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basso (US 20240086070 A1), in view of Huang (US 20260026398 A1) and ALROD (US 20170116070 A1)
Regarding Claim 6, Basso in view of Huang does not explicitly teach:
The method of claim 1, comprising: determining the portion of the virtual block based on a number of program/erase cycles associated with the virtual block.
However, ALROD teaches:
The method of claim 1, comprising: determining the portion of the virtual block based on a number of program/erase cycles associated with the virtual block. (ALROD, [0048] ... a corresponding block health metric may be determined based on usable portions of the particular block (and not based on skipped portions of the particular block). The first block health metric may be determined based on and/or may include a number of program/erase (p/e) cycles of the first block 105)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Basso in view of Huang with health metric based on p/e cycle as taught by ALROD, so in response to a portion of the particular block being identified as at-risk, a particular block of the memory 104 may not be retired (ALROD, [0048])
Regarding Claims 14,
The system of claim 14 performs the same method steps as the method of claim 6, and claim 14 is therefore rejected using the same rationale set forth above in the rejection of claim 6
Regarding Claims 14,
The medium of claim 14 performs the same method steps as the method of claim 6 and part of claim 7, and claim 14 is therefore rejected using the same rationale set forth above in the rejection of claims 6 and 7
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basso (US 20240086070 A1), in view of Huang (US 20260026398 A1) and Yang (US 20250348226 A1)
Regarding Claim 8, Basso in view of Huang does not explicitly teach:
The method of claim 7, comprising prior to detecting the read error: performing the scan operations or the host read operations based on a number of read retry operations before a read operation is successful.
However, Yang teaches:
The method of claim 7, comprising prior to detecting the read error: performing the scan operations or the host read operations based on a number of read retry operations before a read operation is successful. (Yang, [0035] In step 105, it is determined whether a read retry count regarding a number of times a read retry operation has been performed in reading data in the target block exceeds a predetermined read retry count threshold TH3.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Basso in view of Huang with read retry count as taught by Yang, because when threshold is reached, the flow ends, in which the block reliability indication is generated to indicate that target block exhibits weak reliability. (Yang, [0035])
Allowable Subject Matter
Claim 3, 11, 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shukla (US 20220308778 A1): A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.
Muchherla (US 20210191815 A1): A processing device in a memory system maintains a counter to track a number of read operations performed on at least one of a physical block or a plurality of physical blocks of a memory device, wherein the counter is associated with the physical block or the plurality of physical blocks depending on an age of data stored on the physical block. The processing device further determines whether a value of the counter satisfies a first threshold criterion pertaining to the number of read operations performed, and responsive to the value of the counter satisfying the first threshold criterion, performs a data integrity scan to determine a first error rate.
Rayaprolu (US 20230059923 A1): A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
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/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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