DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/172,313, filed on February 10, 2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 18, 2025 was filed on the filing date of the application on January 18, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on January 18, 2025. These drawings are accepted.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 19 recites, “…the corresponding primitive bock in memory…” but should recite, “…the corresponding primitive block in memory…”
Appropriate correction is required.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-17 and 20 of U.S. Patent No.11,861,782. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #19/031,852
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U.S. Patent #11,861,782
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Present Application #19/031,852
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U.S. Patent #11,861,782
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Present Application #19/031,852 Claim 1
U.S. Patent #11,861,782 Claim 1
A control stream decoder for decoding a control stream for a tile group comprising at least two tiles of a rendering space, the control stream decoder comprising:
A control stream decoder for decoding a control stream for a tile group comprising at least two tiles of a rendering space, the control stream decoder comprising:
a fetch module configured to fetch the control stream for the tile group from memory, the control stream comprising one or more fixed length primitive block entries,
each primitive block entry identifying a location in memory of a control data block for a corresponding primitive block; and (Limitation A)
a primitive block entry analyser configured to receive a primitive block entry of the control stream for the tile group,
a primitive block entry analyser configured to receive at least one of the one or more primitive block entries,
the primitive block entry identifying a location in memory of a control data block for a corresponding primitive block,
Limitation A above
and for the received primitive block entry:
and for each received primitive block entry:
(a) determine whether a current tile of the tile group is a valid tile for the corresponding primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile,
(a) in response to determining that a current tile of the tile group is a valid tile for the corresponding primitive block, retrieve the control data block for the corresponding primitive block from the identified location in memory,
(b) in response to determining that the current tile is a valid tile for the corresponding primitive block, retrieve the control data block for the corresponding primitive block from the identified location in memory,
(b) identify, from the retrieved control data block, an address of the corresponding primitive block in memory and primitives of that primitive block relevant for rendering the current tile, and
(c) identify, from the retrieved control data block, an address of the corresponding primitive block in memory and primitives of that primitive block relevant for rendering the current tile, and
(c) output information identifying the address of the corresponding primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.
(d) output information identifying the address of the corresponding primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.
Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
Present Application #19/031,852 Claim 2
U.S. Patent #11,861,782 Claim 1
The control stream decoder of claim 1, wherein
A control stream decoder…comprising: a fetch module configured to fetch the control stream for the tile group from memory,
the primitive block entry has a fixed length.
the control stream comprising one or more fixed length primitive block entries…
Present Application #19/031,852 Claim 3
U.S. Patent #11,861,782 Claim 2
The control stream decoder of claim 1, wherein
The control stream decoder of claim 1, wherein
the primitive block entry comprises valid tile information identifying which tiles of the tile group are valid tiles for the corresponding primitive block.
each primitive block entry comprises valid tile information identifying which tiles of the tile group are valid tiles for the corresponding primitive block.
Present Application #19/031,852 Claim 4
U.S. Patent #11,861,782 Claim 3
The control stream decoder of claim 3, wherein
The control stream decoder of claim 2, wherein
the valid tile information comprises a valid tile mask which comprises a bit for each tile in the tile group which indicates whether that tile is a valid tile for the corresponding primitive block.
the valid tile information comprises a valid tile mask which comprises a bit for each tile in the tile group which indicates whether that tile is a valid tile for the corresponding primitive block.
Present Application #19/031,852 Claim 5
U.S. Patent #11,861,782 Claim 4
The control stream decoder of claim 3, wherein
The control stream decoder of claim 2, wherein
the primitive block entry analyser is configured to determine whether the current tile of the tile group is a valid tile for the corresponding primitive block from the valid tile information of the primitive block entry.
the primitive block entry analyser is configured to determine whether the current tile of the tile group is a valid tile for the corresponding primitive block from the valid tile information of the primitive block entry.
Present Application #19/031,852 Claim 6
U.S. Patent #11,861,782 Claim 5
The control stream decoder of claim 3, further comprising:
The control stream decoder of claim 2, further comprising:
a block skip module configured to, for each of one or more groups of entries of the control stream:
a block skip module configured to, for each of one or more groups of entries of the control stream:
select a portion of the valid tile information for each entry of the group of entries corresponding to the current tile, and
select a portion of the valid tile information for each entry of the group of entries corresponding to the current tile, and
perform an operation on the selected portions to determine whether the current tile is a valid tile for any primitive block corresponding to a primitive block entry in the group of entries;
perform an operation on the selected portions to determine whether the current tile is a valid tile for any primitive block corresponding to a primitive block entry in the group of entries;
wherein the primitive block entry analyser only receives primitive block entries in a group of entries of the one or more groups of entries if a result of the operation for that group of entries indicates that the current tile is a valid tile for at least one primitive block corresponding to a primitive block entry in the group of entries.
wherein the primitive block entry analyser only receives primitive block entries in a group of entries of the one or more groups of entries if a result of the operation for that group of entries indicates that the current tile is a valid tile for at least one primitive block corresponding to a primitive block entry in the group of entries.
Present Application #19/031,852 Claim 7
U.S. Patent #11,861,782 Claim 6
The control stream decoder of claim 6, wherein:
The control stream decoder of claim 5, wherein:
the valid tile information for each entry comprises a valid tile mask with a bit for each tile of the tile group;
the valid tile information for each entry comprises a valid tile mask with a bit for each tile of the tile group;
the selected portion of the valid tile information for each entry is the bit of the valid tile mask that corresponds to the current tile; and
the selected portion of the valid tile information for each entry is the bit of the valid tile mask that corresponds to the current tile; and
the operation that is performed on the selected portions is an OR operation.
the operation that is performed on the selected portions is an OR operation.
Present Application #19/031,852 Claim 8
U.S. Patent #11,861,782 Claim 7
The control stream decoder of claim 7, wherein
The control stream decoder of claim 5, wherein
the control stream comprises one or more other types of entries and each of the one or more other types of entries comprises valid tile information that indicates that none of the tiles of the tile group are valid tiles.
the control stream comprises one or more other types of entries and each of the one or more other types of entries comprises valid tile information that indicates that none of the tiles of the tile group are valid tiles.
Present Application #19/031,852 Claim 9
U.S. Patent #11,861,782 Claim 8
The control stream decoder of claim 1, wherein
The control stream decoder of claim 1, wherein
the control stream comprises one or more other types of entries, and the control stream decoder further comprises an entry type analyser configured to:
wherein the control stream comprises one or more other types of entries, and the control stream decoder further comprises an entry type analyser configured to:
receive one or more entries of the control stream, determine a type of each of the one or more received entries, and in response to determining that a received entry is a primitive block entry, forward the primitive block entry to the primitive block entry analyser.
receive one or more entries of the control stream, determine a type of each of the one or more received entries, and in response to determining that a received entry is a primitive block entry, forward the primitive block entry to the primitive block entry analyser.
Present Application #19/031,852 Claim 10
U.S. Patent #11,861,782 Claim 9
The control stream decoder of claim 9, wherein
The control stream decoder of claim 8, wherein
each entry of the control stream comprises one or more entry type bits and the entry type analyser is configured to determine the type of each entry based on the one or more entry type bits of that entry.
each entry of the control stream comprises one or more entry type bits and the entry type analyser is configured to determine the type of each entry based on the one or more entry type bits of that entry.
Present Application #19/031,852 Claim 11
U.S. Patent #11,861,782 Claim 1
The control stream decoder of claim 8, comprising
A control stream decoder…comprising:
a fetch module configured to fetch the control stream for the tile group from memory.
a fetch module configured to fetch the control stream for the tile group from memory…
Present Application #19/031,852 Claim 12
U.S. Patent #11,861,782 Claim 10
The control stream decoder of claim 9, wherein:
The control stream decoder of claim 8, wherein:
the control stream is stored in memory in a plurality of control stream blocks, and a last entry in each control stream block, other than the last control stream block, is a link entry which identifies a location of a next control stream block in memory;
the control stream is stored in memory in a plurality of control stream blocks, and a last entry in each control stream block, other than the last control stream block, is a link entry which identifies a location of a next control stream block in memory;
the control stream decoder further comprises a link entry analyser configured to receive one or more link entries and, for each received link entry, extract the location in memory of the next control stream block from that link entry and provide the extracted location to the fetch module; and
the control stream decoder further comprises a link entry analyser configured to receive one or more link entries and, for each received link entry, extract the location in memory of the next control stream block from that link entry and provide the extracted location to the fetch module; and
the entry type analyser is configured to, in response to determining that a received entry is a link entry, forward the link entry to the link entry analyser.
the entry type analyser is configured to, in response to determining that a received entry is a link entry, forward the link entry to the link entry analyser.
Present Application #19/031,852 Claim 13
U.S. Patent #11,861,782 Claim 11
The control stream decoder of claim 9, wherein:
The control stream decoder of claim 8, wherein:
each primitive block entry comprises a data pointer that identifies the location in memory of the control data block for the corresponding primitive block;
each primitive block entry comprises a data pointer that identifies the location in memory of the control data block for the corresponding primitive block;
the control stream comprises at least one control data base address entry which specifies at least a portion of a control data base address;
the control stream comprises at least one control data base address entry which specifies at least a portion of a control data base address;
the control stream decoder further comprises a control data base address entry analyser configured to receive one or more control data base address entries and, for each received control data base address entry, extract at least a portion of a control data base address from that control data base address entry, and update a current control data base address based on the extracted at least a portion of the control data base address;
the control stream decoder further comprises a control data base address entry analyser configured to receive one or more control data base address entries and, for each received control data base address entry, extract at least a portion of a control data base address from that control data base address entry, and update a current control data base address based on the extracted at least a portion of the control data base address;
the primitive block entry analyser is configured to generate an address of a control data block in memory from a combination of the current control data base address and the data pointer of the primitive block entry; and
the primitive block entry analyser is configured to generate an address of a control data block in memory from a combination of the current control data base address and the data pointer of the primitive block entry; and
the entry type analyser is configured to, in response to determining that a received entry is a control data base address entry, forward the control data base address entry to the control data base address entry analyser.
the entry type analyser is configured to, in response to determining that a received entry is a control data base address entry, forward the control data base address entry to the control data base address entry analyser.
Present Application #19/031,852 Claim 14
U.S. Patent #11,861,782 Claim 12
The control stream decoder of claim 13, wherein
The control stream decoder of claim 11, wherein
each data pointer comprises an offset into a portion of the memory identified by the current control data base address.
each data pointer comprises an offset into a portion of the memory identified by the current control data base address.
Present Application #19/031,852 Claim 15
U.S. Patent #11,861,782 Claim 13
The control stream decoder of claim 13, wherein
The control stream decoder of claim 11, wherein
each control data base address entry specifies a complete control data base address.
each control data base address entry specifies a complete control data base address.
Present Application #19/031,852 Claim 16
U.S. Patent #11,861,782 Claim 14
The control stream decoder of claim 13, wherein
The control stream decoder of claim 11, wherein
each control data base address entry specifies only a portion of a complete control data base address.
each control data base address entry specifies only a portion of a complete control data base address.
Present Application #19/031,852 Claim 17
U.S. Patent #11,861,782 Claim 15
The control stream decoder of claim 9, wherein:
The control stream decoder of claim 8, wherein:
the control stream further comprises a termination entry which identifies an end of the control stream, the termination entry being a last entry in the control stream, and
the control stream further comprises a termination entry which identifies an end of the control stream, the termination entry being a last entry in the control stream, and
the entry type analyser is configured to, in response to determining that a received entry is a termination entry, determine an end of the control stream has been reached.
the entry type analyser is configured to, in response to determining that a received entry is a termination entry, determine an end of the control stream has been reached.
Present Application #19/031,852 Claim 18
U.S. Patent #11,861,782 Claim 16
The control stream decoder of claim 1, wherein
The control stream decoder of claim 1, wherein
the control data block comprises information identifying which primitives of the corresponding primitive block intersect each tile of the tile group and the primitive block entry analyser is configured to identify, from the information identifying which primitives in the corresponding primitive block intersect each tile of the tile group, the primitives of that primitive block relevant for rendering the current tile.
each control data block comprises information identifying which primitives of the corresponding primitive block intersect each tile of the tile group and the primitive block entry analyser is configured to identify, from the information identifying which primitives in the corresponding primitive block intersect each tile of the tile group, the primitives of that primitive block relevant for rendering the current tile.
Present Application #19/031,852 Claim 19
U.S. Patent #11,861,782 Claim 17
The control stream decoder of claim 1, wherein
The control stream decoder of claim 1, wherein
the control data block comprises information identifying an address of the corresponding primitive block in memory and the primitive block entry analyser is configured to identify, from the information identifying an address of the corresponding primitive bock in memory, an address of the primitive block in memory.
each control data block comprises information identifying an address of the corresponding primitive block in memory and the primitive block entry analyser is configured to identify, from the information identifying an address of the corresponding primitive bock in memory, an address of the primitive block in memory.
Present Application #19/031,852 Claim 20
U.S. Patent #11,861,782 Claim 20
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of the control stream decoder as set forth in claim 1, which when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the control stream decoder.
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of the control stream decoder as set forth in claim 1, which when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the control stream decoder.
Allowable Subject Matter
Claims 1-20 would be allowable if the Double Patenting rejection set forth above may be overcome.
The following is a statement of reasons for the indication of allowable subject matter:
The present invention relates to a system and method of decoding a control stream for a tile group of a rendering space.
Closest prior art includes:
Yang (US 2011/0304608)(cited in the Information Disclosure Statement (IDS) filed January 18, 2025), which discloses a three-dimensional (3D) computer system and method of subdividing an image into a plurality of rectangular areas and primitives which may be visible in the image are assigned to respective ones of a plurality of primitive blocks, determining which primitive blocks contain primitives which intersect each rectangular area, grouping the rectangular areas into a plurality of fixed size groups, deriving control stream data for each of the fixed size groups, where this control stream data includes data which determines which primitive blocks are required to render the rectangular areas in each respective fixed size group, and then using the control stream data to render the image for display; and
Yang et al. (US 2017/0316604)(also cited in the IDS filed) disclose a method of generating a control stream for a tile, the method including determining whether a primitive falls within a tile based on positions of samples within each pixel, and if it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile, e.g. an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile.
Although the prior art of record discloses similar features of the claimed invention
as noted above, the prior art cited fails to teach or suggest, singly or combined, the limitations of independent claims 1 and 20 as recited as a whole.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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