DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20020024622 A1 (Murade, Masao).
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Per claims 1 and 20, Murade teaches a display panel, comprising: a first base substrate [10]; and a plurality of sub-pixel structures arranged in an array on the base substrate [14], wherein each of the plurality of sub-pixel structure comprises: a thin film transistor disposed on the base substrate [1-3], the thin film transistor comprising a source and a drain [1 and contacting potion of 14]; an insulating layer disposed on a side of the thin film transistor distal from the base substrate [13], a first via hole being formed in the insulating layer [contact hole 4]; a pixel electrode disposed on a side of the insulating layer distal from the base substrate [14], the pixel electrode being electrically connected to either the source or the drain through the first via hole [see figure 6]; and a light shielding pattern disposed on a side, proximal to the base substrate, of the source and the drain [7], wherein the light shielding pattern comprises a plurality of light shielding portions [horizontal portions of shielding layer 7] and a plurality of connecting portions [vertical portions of shielding layer 7]; wherein the plurality of light shielding portions are connected to the plurality of connecting portions [see figure 7], each of the plurality of light shielding portions is extended along a first direction [horizonal direction], and the plurality of light shielding portions are arranged along a second direction [vertical direction]; and the plurality of connecting portions are disposed on two sides of the light shielding portion in the second direction [see figure 7], each of the plurality of connecting portions is extended along the second direction [see figure 7], and the plurality of connecting portions are arranged along the first direction; wherein the second direction intersects the first direction [see figure 7].
Per claim 4, Murade teaches the substrate according to claim 1, wherein the thin film transistor further comprises an active layer [1] and a gate line [2]; wherein the active layer is disposed on the side, proximal to the base substrate , of the source and the drain [see figure 6], and the active layer is electrically connected to the source and the drain [see figure 6]; the gate line is disposed on a side of the active layer distal from the base substrate [see figure 6], and an orthographic projection of the gate line on the base substrate is overlapped with an orthographic projection of the active layer on the base substrate [see figure 7]; and the light shielding pattern is disposed on a side of the active layer proximal to the base substrate [see figure 6], wherein an orthographic projection of the light shielding pattern on the base substrate is overlapped with the orthographic projection of the active layer on the base substrate [see figure 7], and a surface of the light shielding pattern facing the base substrate is a reflective surface [see paragraph 0121: “a first light shielding film 7 (an area shaded with parallel lines with a positive gradient in FIG. 1) which is made of a metal such as tungsten, titanium, chromium, tantalum or molybdenum, or their alloy.”]
Per claim 18, Murade teaches the substrate according to claim 1, wherein the sub-pixel structure further comprises a filling block disposed at the first via hole and protruding from the first via hole.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20020024622 A1 (Murade, Masao).
Per claim 5, Murade teaches the substrate according to claim 4, but lacks the light shielding pattern comprises: a first base, and a reflective layer disposed on a surface of the first base facing the base substrate; wherein a material of the first base comprises at least one of titanium, tin and molybdenum, a material of the reflective layer comprises aluminum, and a material of the light shielding pattern comprises an aluminum alloy. However, official notice is taken that it would have been a matter of routine skill in the art to configure the light shielding with a first base, and a reflective layer disposed on a surface of the first base facing the base substrate; wherein a material of the first base comprises at least one of titanium, tin and molybdenum, a material of the reflective layer comprises aluminum, and a material of the light shielding pattern comprises an aluminum alloy to improve adhesion of the shielding layer to the substrate. Therefore, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art.
Per claim 18, Murade teaches the substrate according to claim 1, but lacks the sub-pixel structure further comprises a filling block disposed at the first via hole and protruding from the first via hole. However, official notice is taken that it would have been a matter of routine skill in the art to configure the sub-pixel structure to further comprise a filling block disposed at the first via hole and protruding from the first via hole to improve image contrast by reducing light leakage. Therefore, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 2-3, 6-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Per claim 2, the prior art teaches the substrate according to claim 1, wherein the thin film transistor further comprises an active layer and a gate line [1 and 2]; wherein the active layer is disposed on the side, proximal to the base substrate, of the source and the drain, and the active layer is electrically connected to the source and the drain [see figure 6]; and the gate line is disposed on a side of the active layer distal from the base substrate [see figure 6], and an orthographic projection of the gate line on the base substrate is overlapped with an orthographic projection of the active layer on the base substrate [see figure 7]. In combination with the limitations above, the prior art does not teach an orthographic projection of a center of the first via hole on the base substrate is between orthographic projections of two active layers adjacent in a first direction on the base substrate, the first direction being parallel to an extension direction of the gate line.
Per claim 6, the prior art teaches the substrate according to claim 4, wherein the active layer comprises a source contact portion, a drain contact portion, and an intermediate portion disposed between the source contact portion and the drain contact portion [see figure 6]; and the orthographic projection of the active layer on the base substrate is at least partially overlapped with the orthographic projection of the light shielding pattern on the base substrate [see figure 6]; an extension direction of the gate line being parallel to the first direction [see figure 7]. In combination with the limitations above, the prior art does not teach a size of the source contact portion in the first direction and a size of the drain contact portion in the first direction are greater than a size of the intermediate portion in the first direction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES A DUDEK whose telephone number is (571)272-2290. The examiner can normally be reached Monday-Thursday 6:30-4:30 MT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES A DUDEK/Primary Examiner, Art Unit 2871
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