DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 17 - 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 11, it is unclear where are first and second switching pads positioned with respect to the control circuit?
As to claim 17, applicant claimed performing a stress test on a gate of a power transistor. However, the series of steps for claimed performing a stress test on a gate of a power transistor are not defined. It is unclear how applicant is performing a stress test on a gate of a power transistor?
As to claim 18, applicant claimed measuring a leakage current on the first contact pad or on a third contact pad. However, the series of steps for claimed measuring a leakage current on the first contact pad or on a third contact pad are not defined.
Claim 20 recites the limitation "the first and second switching pads" in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim.
Claims 18 - 20 are rejected by virtue of the dependency on claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 6, 8, 9 and 12 - 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Giunta et al. (2023/0017307).
As to claim 1, Giunta et al. (hereinafter Giunta) discloses a driver device comprising: a first contact pad (the M0 transistor has a contact pad, e.g. (source metallization or connection line)); a second contact pad (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]); a control circuit (104); and a power transistor (nMOS power transistor M0, [0024]) having: a gate (G0) coupled to the control circuit (“pre-driver 102”, “controller 104”, [0018]), and a source (“n-type semiconductor region S0” of MO, [0016]) coupled to the first contact pad (the M0 transistor has a contact pad, e.g. (source metallization or connection line)), wherein the control circuit (104) is coupled to the second contact pad (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]), and wherein the first (the M0 transistor has a contact pad, e.g. (source metallization or connection line)) and second (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]) contact pads are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate (G0) of the power transistor (nMOS power transistor M0), and the first and second contact pads are configured to be coupled to each other when the power transistor (nMOS power transistor M0) and control circuit (102, 104) are encapsulated [0019], (Fig. 1 and 3).
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As to claim 12, Giunta discloses a driver device comprising: a power electronic circuit (100) including a first contact pad (the M0 transistor has a contact pad, e.g. (source metallization or connection line)); a second contact pad (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]); a control circuit (104); and a power transistor (nMOS power transistor M0, [0024]) having: a gate (G0) coupled to the control circuit (“pre-driver 102”, “controller 104”, [0018]), and a source (“n-type semiconductor region S0” of MO, [0016]) coupled to the first contact pad (the M0 transistor has a contact pad, e.g. (source metallization or connection line)), wherein the control circuit (104) is coupled to the second contact pad (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]), and wherein the first (the M0 transistor has a contact pad, e.g. (source metallization or connection line)) and second (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]) contact pads are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate (G0) of the power transistor (nMOS power transistor M0), and the first and second contact pads are configured to be coupled to each other when the power transistor (nMOS power transistor M0) and control circuit (102, 104) are encapsulated [0019], (Fig. 1 and 3).
As to claims 2 and 13, Giunta discloses that the power transistor (nMOS power transistor, [0024]) and the control circuit (104) are high-side components of the power electronic circuit, and the first (the MO transistor has a contact pad) and second contact pads (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]) are configured to receive different electrical supply potentials when the power electronic circuit is in the configuration for stress testing the gate (G0) of the power transistor (nMOS power transistor), (Fig. 1 and 3), [0024].
As to claims 3 and 14, Giunta discloses that the power transistor (M1, nMOS) and the control circuit are low-side components [0017] of the power electronic circuit (102), and wherein the first and second contact pads are configured to receive different electrical reference potentials when the power electronic circuit is in the configuration for stress testing the gate (G1) of the power transistor (the power transistor M1 and the control circuit 102 as such also represent low-side components), (Fig. 1 and 3), [0017], [0026].
As to claim 6, Giunta discloses that the control circuit includes a CMOS inverter having an output coupled to the gate of the power transistor, or the power transistor is a MOSFET [0015] and [0016].
As to claim 8, Giunta discloses an encapsulation element ([0019], Fig. 1, 3).
As to claim 9, Giunta discloses that a first electrical connector electrically coupling the first (the M0 transistor has a contact pad, e.g. (source metallization or connection line) and second contact pads (metallization of a connection line, at the input of the “PWM_HS” signal, [0018]) (Fig. 1, 3).
Allowable Subject Matter
Claims 4 – 5, 7, 10 and 15 - 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant s disclosure.
Poechmueller (2006/0061378) is cited for its disclosure of a semiconductor device with test circuit disconnected from power supply connection.
Chen et al. (5,659,462) is cited for its disclosure of an encapsulated, integrated power magnetic device and method of manufacture therefor.
Otremba et al. (9,952,273) is cited for its disclosure of a compound semiconductor device including a sensing lead.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to REENA AURORA whose telephone number is (571)272-2263. The examiner can normally be reached M-F: 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at 5712705628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/REENA AURORA/Primary Examiner, Art Unit 2858
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