Prosecution Insights
Last updated: July 17, 2026
Application No. 19/033,343

HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE

Non-Final OA §102
Filed
Jan 21, 2025
Priority
Dec 17, 2014 — continuation of 11/321,263 +2 more
Examiner
HUYNH, KIM T
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
582 granted / 707 resolved
+27.3% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
18 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
63.7%
+23.7% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 707 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 2. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Solihin (Pub. No. US2015/0331831) As per claims 1,9,15, Solihin discloses a processor comprising: a plurality of processing elements (fig.1, processor cores 121) to perform a corresponding plurality of operations based on program code (paragraph 66, signal include sets of executable instructions); a plurality of router circuits (fig.1, routers 122) corresponding to the plurality of processing elements, each router circuit including: a plurality of configurable communication ports (fig.3, input port 310a, output port 320a) to support packet-switched connections (paragraph 27, line 3, a circuit-switched connection setup packet 202) and circuit-switched connections with other router circuits of the plurality of router circuits(figure 3 & paragraph 30-32, a hybrid router with circuit-switched implement packet switching between the input and output ports to/from cores 121.), each configurable communication port to be configured as either a packet-switched communication port or a circuit-switched communication port (paragraph 31, lines 1-2, each of input ports 310 may be associated with a circuit-switched virtual channel 311 and a packet-switched virtual channel 312), the configurable communication port to be configured as a circuit-switched communication port based on configuration data received in a packet by the router circuit(paragraph 31, line 8, network router 122 may be configured with input and output buffering), a processing element port to couple the router circuit to a corresponding processing element of the plurality of processing elements(fig.1, processor cores 121), and crossbar switching logic (fig.3, crossbar switch 330) to provide inter-port communication paths within the router circuit between the processing element port and the plurality of configurable communication ports (paragraph 31, line 10, Crossbar switch 330 may interconnect input ports 310 with output ports 320); and an interconnect network (fig.1, network-on-chip 108) coupled to the plurality of router circuits (fig.1, routers 122), the interconnect network to communicate data in accordance with the circuit-switched connections and packet-switched connections between the router circuits (paragraph 20, routers configured to pre-reserve circuit-switched connections between a source node and a destination node before requested data are available for transmission from the source node to the destination node.) As per claims 2, 10, Solihin discloses wherein the configuration data comprises an indication of whether circuit-switched operation is enabled (paragraph 33, configured to perform one or more functions, acts, or operations that enable a circuit-switched connection to be pre-reserved between a source node and a destination node in NoC 108). As per claims 3, 11, 16, Solihin discloses wherein the plurality of router circuits are arranged in a grid and the plurality of configurable communication ports are oriented in different directions within the grid(figure 3 & paragraph 30-32, a hybrid router with circuit-switched implement packet switching between the input and output ports to/from cores 121). Asper claim 14 wherein the plurality of configurable communication ports include a first communication port (fig.3, input port 310a, output port 320a) to transmit in a first direction, a second communication port (paragraph 66, signal with different sources include sets of executable instructions) to transmit in a second direction opposite the first direction, a third communication port (fig.3, input port 310b, output port 320b) to transmit in a third direction, and a fourth communication port to transmit in a fourth direction opposite the third direction (paragraph 34, lines 8-10, routing and arbitration controller 340, to pre-reserve a circuit-switched connection with the appropriate ports in the opposite direction of the request message.) As per claims 5, 12, 17, Solihin discloses wherein based on the packet, the router circuit is to establish a circuit-switched connection between the processing element port and multiple configurable communication ports of the plurality of configurable communication ports (paragraph 32, network router 122 is depicted in FIG. 3 with a circuit-switched channel 350 that couples input port 310A with output port 320B). As per claims 6, 13, 18, Solihin discloses wherein the plurality of configurable communication ports of each router circuit are configurable to simultaneously support both circuit-switched operation and packet-switched operation (paragraph 31, routing and arbitration controller 340 can be configured to resolve conflicts between simultaneous requests for the same output port 320). As per claims 7, 14,19, Solihin discloses wherein a first one or more configurable communication ports of the plurality of configurable communication ports are configurable for a first circuit switched channel while a second one or more configurable communication ports of the plurality of configurable communication ports are configurable for a first circuit switched channel (paragraph 31, network router 122 may be configured with different numbers of circuit-switched virtual channels and packet-switched virtual channels. Each packet-switched virtual channel 322 may include a buffer 323 for storing one or more units of communication until the next portion of NoC 108 is available for data transmission.) As per claims 8, 20, Solihin discloses wherein one or more configurable communication ports of the plurality of configurable communication ports are to communicate at a first maximum bandwidth when fully utilized and the processing element port is to communicate at a second maximum bandwidth when fully utilized, the second maximum bandwidth higher than the first maximum bandwidth (paragraph 50, bandwidth utilization in NoC 108 may be enhanced, since start time 521B of pre-reservation window 520B may not start significantly earlier than data transmission 404A is likely to arrive at the intermediary node.) 3. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Lesartre et al. [US Patent No. US8,732,331] discloses a crossbar switch allowing point-to-point device interconnections to be rerouted on the fly. This dynamic point-to-point connection behavior can result in operations being performed simultaneously by system devices. Alvarez Lcaza Rivera et al. [Pub. No. US2016/0224889] discloses the switches 100 of the chip circuit 100 are interconnected via multiple data paths (e.g., signal lines). Conclusion 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV]. The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K. T. H./ Examiner, Art Unit 2184 /HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
Read full office action

Prosecution Timeline

Jan 21, 2025
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
90%
With Interview (+7.3%)
2y 8m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 707 resolved cases by this examiner. Grant probability derived from career allowance rate.

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