DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2021/0012711 A1 to Huang et al.
As to claim 1, Huang discloses a display device, comprising:
a display panel including pixels, each pixel having a driving transistor for generating a driving current, a light-emitting element connected between a first node and an input terminal of a low-potential driving voltage and emitting light according to the driving current, and a first transistor connected between the driving transistor and the first node (Fig. 1, 4 and 6A-6D, paragraphs 0034 and 0044-0059, where pixels (22) have a drive transistor (T2), light-emitting diode (304), ground power supply voltage, which is the low-potential driving voltage (VSSEL), and a first transistor (T5) connected between the driving transistor (T2) and first node (Node4)); and
a gate driver configured to generate an emission control signal of a gate-on voltage and supply the emission control signal of the gate-on voltage to a gate electrode of the first transistor (Fig. 1, 4 and 6A-6D, paragraphs 0048-0050, where transistor (T5) receives emission control signal (EM1)),
wherein a magnitude of the gate-on voltage of the emission control signal changes according to a luminance (Fig. 1, 4 and 6A-9, paragraphs 0048-0062, where the emission control signal (EM1) controls the brightness of display (14)).
As to claim 2, Huang discloses the display device, wherein the low-potential driving voltage varies based on luminance bands of the pixels of the display panel (Fig. 1, 4, 6A-13, paragraphs 0047-0057, where the low-potential driving voltage (VSSEL) may vary).
As to claim 3, Huang discloses the display device, wherein the gate driver is configured to adjust the magnitude of the gate-on voltage of the emission control signal, based on the low-potential driving voltage of the light-emitting element for each luminance band of the pixels of the display panel (Fig. 1, 4, 6A-12, paragraphs 0048-0071, where the brightness is controlled by emission control signals (EM1, EM2) and each luminance band has a different voltage as shown in Fig. 12).
As to claim 4, Huang discloses the display device, wherein the low-potential driving voltage varies based on an interpolation between the luminance bands (Fig. 13, paragraphs 0072-0074, where interpolation is used to determine the driving voltage).
As to claim 5, Huang discloses the display device, wherein the gate driver is configured to adjust the magnitude of the gate-on voltage of the emission control signal, based on the low-potential driving voltage of the light-emitting element for each luminance band group of the display panel (Fig. 1, 4, 6A-12, paragraph 0048-0071, where the brightness is controlled by emission control signals (EM1, EM2) and each luminance band has a different voltage as shown in Fig. 12).
As to claim 6, Huang discloses the display device, wherein the gate driver is configured to:
determine a sum the low-potential driving voltage, an anode reset voltage to the light-emitting element, and a voltage difference between a voltage of the gate electrode and a voltage of a source electrode of the first transistor as the gate-on voltage of the emission control signal (Fig. 1, 4, 6A-9, paragraphs 0048-0062, where the low-potential driving voltage is (VSSEL), the anode reset voltage is (Vini), the first transistor is (T5), and the gate-on voltage is emission control signal (EM1)); and
apply the gate-on voltage of the emission control signal to the gate electrode of the transistor (Fig. 1, 4 and 6A-6D, paragraphs 0048-0050, where transistor (T5) receives emission control signal (EM1)).
As to claim 7, Huang discloses the display device, wherein as a luminance level of the pixels of the display panel decreases, the magnitude of the gate-on voltage to be applied to the gate electrode of the first transistor increases (Fig. 1, 4, 6A-12, paragraphs 0048-0071, where the brightness is controlled by emission control signals (EM1, EM2) and each luminance band has a different voltage as shown in Fig. 12) and
wherein as a luminance level of the pixels of the display device decreases, the magnitude of the low-potential driving voltage increases (Fig. 1, 4, 6A-13, paragraphs 0047-0057, where the low-potential driving voltage (VSSEL) may vary).
As to claim 8, Huang discloses the display device, further comprising a power supply for supplying power to the display panel,
wherein, in response to the magnitude of the gate-on voltage of the emission control signal being smaller than a first threshold voltage, the power supply is configured to multiply the gate-on voltage of the emission control signal by a first constant (Fig. 1, 4, 6A-9, paragraphs 0048-0062, where the emission control signal (EM1) is adjusted by a constant), and
wherein the gate driver is configured to apply a voltage of a value obtained by multiplying the gate-on voltage of the emission control signal by the first constant to the gate electrode of the first transistor (Fig. 1 and 4, paragraphs 0047-0049, where DDIC (16), row driver circuitry (18) and/or column driver circuitry (20) adjusts emission control signal (EM1) via terminal (314) to first transistor (T5)).
As to claim 9, Huang discloses the display device, wherein:
in response to the magnitude of the gate-on voltage of the emission control signal being greater than the first threshold voltage, the power supply is further configured to multiply the gate-on voltage of the emission control signal by a second constant (Fig. 1, 4, 6A-9, paragraphs 0048-0062, where the emission control signal (EM1) is adjusted by a constant); and
the gate driver is configured to apply a voltage of a value obtained by multiplying the gate-on voltage of the emission control signal by the second constant to the gate electrode of the first transistor (Fig. 1 and 4, paragraphs 0047-0049, where DDIC (16), row driver circuitry (18) and/or column driver circuitry (20) adjusts emission control signal (EM1) via terminal (314) to first transistor (T5)).
As to claim 10, Huang discloses the display device, wherein the first constant is greater than the second constant (Fig. 1, 4, 6A-9, paragraphs 0048-0062, where the emission control signal (EM1) is adjusted by a constant, which may be of any value).
As to claim 11, Huang discloses the display device, wherein:
the power supply is configured to adjust the magnitude of the voltage to be applied to the gate electrode of the first transistor, based on the low-potential driving voltage of the light-emitting element of the pixels (Fig. 1, 4, 6A-6D, paragraphs 0047-0059, where DDIC (16), row driver circuitry (18) and/or column driver (20) adjusts the emission control signal (EM1) via terminal (314) to first transistor (T5)); and
the low-potential driving voltage varies based on an interpolation between luminance bands of the pixels of the display panel (Fig. 4, 13 and 14, paragraphs 0047-0049 and 0072-0080, where the power supply voltage (VDDEL) is adjusted by using interpolation as shown in Fig. 13).
Response to Arguments
Applicant's arguments filed 12/3/2025 have been fully considered but they are not persuasive.
Applicant argues, with respect to claim 1, on pages 6-7, lines 17-23, Huang fails to disclose, the “first transistor” and “gate-on voltage of the emission control signal”. Examiner disagrees as Huang discloses, “first transistor” (Fig. 1, 4 and 6A-6D, paragraphs 0034 and 0044-0059, first transistor (T5)) and “gate-on voltage of the emission control signal” (Fig. 1, 4 and 6A-6D, paragraphs 0048-0050, where transistor (T5) receives emission control signal (EM1)).
Applicant argues, with respect to claims 2-11, on pages 7-8, lines 24-2, since these claims are dependent on claim 1, they are allowable. Examiner disagrees for the reasons stated above.
Applicant argues, on page 8, lines 3-7, the application is in condition for allowance. Examiner disagrees for the reasons stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEETA YODICHKAS whose telephone number is (571)272-9773. The examiner can normally be reached Monday-Friday 9-5.
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ANEETA YODICHKAS
Primary Examiner
Art Unit 2627
/ANEETA YODICHKAS/ Primary Examiner, Art Unit 2627