DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The new title is accepted.
Response to Amendment
Applicant's arguments filed 06/16/2026 have been fully considered
In regards to the rejections pertaining to 35 U.S.C. 101, necessary amendments have been made to overcome the rejection. The rejection has been withdrawn.
In regards to the rejections pertaining to 35 U.S.C. 102, the argument pertaining to the golden signature is persuasive and the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made under 35 U.S.C. 103 in view of Dhonde (see below).
In regards to the rejections pertaining to 35 U.S.C. 103, the arguments were full considered. The Applicant argues that Kamran fails to disclose “operation units inside the core;” however, the Examiner respectfully disagrees. On page 258, III. Test Timing, Kamran teaches that the local test controller isolates the processing core by putting it in test mode and captures the response from the processing core through the use of local MISRs. This indicate that the testing is occurring by the processing core. In order for testing to occur, it would inherently need operation units. The Examiner will also point to Hukerikar (see below) which recites a more detailed implementation in which an arithmetic logic unit of a processor is used in order to conduct such testing.
The Applicant argues that Kamran fails to disclose using a comparison in order to determine the test result as opposed to the golden signature claimed in the newly amended claim limitation. The Examiner agrees and withdraws the rejection. However, upon further consideration, a new ground of rejection is made in view of Dhonde (see below). The Applicant argues that “even if Dhonde does not use a golden reference for testing, the test in Dhonde still does not involve a technical solution that determines whether the processor test passes by comparing the operation results of operation units of the same type” (page 19). Further, the Applicant argues that Dhonde “does not disclose the technical solution of determining whether the processor test passes by comparing the operation results, nor its technical effects.” The Applicant also argues that “the test cases provided by Dhonde do not involve the application scenario of testing the operation function of a processor, let alone the technical solution of obtaining a test result by comparing operation results as in the present disclosure.” However, they are moot points since Dhonde is used to teach only that comparing a test result is a known substitution to “a golden signature” (Non-Final Rejection Office Action 03/27/26, top of page 26). It is not relied upon to teach any of the other specifics of the claim limitations.
The Applicant further discloses that the additional prior art Seiler does not disclose this deficiency. However, it is a moot point since Seiler is not relied upon for the 35 U.S.C. 103 rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, 13, 16, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamran et al (“Online Periodic Test Mechanism for Homogeneous Many-core Processors”, Proceedings of 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013) in view of Hukerikar et al (US 20240402250 A1) in further view of Dhonde et al (US 12455813 B1)
Per claim 1, Kamran teaches
A processor testing method, wherein the processor comprises at least one processor core, the processor core comprises operation units, and the method comprises (page 258, “III. Test Timing” section, the local test controller isolates the processing core by putting it in test mode and captures the response from the processing core through the use of local MISRs. This indicates that the testing is occurring in the processing core. In order for testing to occur, it would inherently need operation units)
Obtaining, by the processor core, an initialization instruction for implementing a self-test of the processor (page 258, “D. Local Test Controllers (LTC)” section, the local test controller (LTC) receives the test-snippet; Abstract, the subject matter is on self-testing)
Initializing, by the processor core, a preset parameter in a storage space to a test input value based on the initialization instruction; wherein the preset parameter refers to a parameter that is currently input to the operation units (page 258, “D. Local Test Controllers (LTC)” section, the local test controllers (LTC) executes the test-snippet. It is the Examiner’s interpretation that it is implied that the test is initialized during the process of executing the testing which requires obtaining test input values)
Controlling, by the processor core, the operation units to perform operation on the test input value, to obtain operation results; …; and (page 258, “D. Local Test Controllers (LTC)” section, the test-snippet is executed and the output is generated)
Kamran fails to recite
wherein controlling, by the processor core, the operation units to perform operation on the test input value, to obtain operation results comprises: controlling the operation units of the same type to perform operation on the test input value to obtain the operation results respectively corresponding to the operation units of the same type
However, Hukerikar teaches
wherein controlling, by the processor core, the operation units to perform operation on the test input value, to obtain operation results comprises: controlling the operation units of the same type to perform operation on the test input value to obtain the operation results respectively corresponding to the operation units of the same type ([0050] “As an example, a test pattern 206 that tests an arithmetic logic unit (“ALU”) of processor 208 may cause processor 208 to perform one or more integer addition and/or subtraction operations to generate one or more output values as results; the ALU is the operation unit)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Kamran with the teaching of Hukerikar because Hukerikar offers a more detailed implementation detail of the testing being conducted in Kamran by reciting the specific operation unit that is present in order to conduct a specific arithmetic testing of the operation unit.
Kamran in view of Hukerikar fails to recite
Determining, by the processor core, a test result based on the operation results, wherein the test result is obtained by comparing the operation results respectively corresponding to the operation units of the same type with each other
However, Dhonde teaches
the test result is obtained by comparing the operation results respectively corresponding to the operation units of the same type with each other (Dhonde, col 10 lines 43-50).
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Kamran in view of Hukerikar with the teaching of Dhonde because Kamran recites finding a test result based on the test result’s comparison to “a golden signature” (page 258, “D. Local Test Controllers (LTC)” section, the output is compared against “a golden signature” and the pass/fail result is stored in a local flip-flop). Dhonde teaches that using a previous test run result instead of “a golden signature” is a known substitution (Dhonde, col 10 lines 43-50).
Per claim 9, Kamran in view of Hukerikar in further view of Dhonde teaches
The method according to claim 1, wherein the obtaining, by the processor core, an initialization instruction comprises:
obtaining an immediate number initialization instruction, wherein the immediate number initialization instruction comprises the test input value to be written into the storage space. (page 258, “D. Local Test Controllers (LTC)” section, LTC receives a test-snippet and stores it in a local buffer and then executes the test-snippet. It is the Examiner’s interpretation that writing into the storage space is taught by this storing in the local buffer).
Per claim 13, Kamran in view of Hukerikar in further view of Dhonde teaches
The method according to claim 1, wherein the determining, by the processor core, a test result based on the operation results comprising:
determining a status indicating whether or not the operation result satisfies a preset condition; (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the output is compared against the “golden signature”)
in response to that the status is that the preset condition is satisfied, determining that the test result is test succeeded; and (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result of the comparison is stored in the pass/fail result in a local flip-flop. It is the Examiner’s interpretation that if the output matches the “golden signature,” the result indicating “pass” will be stored in the local flip-flop).
in response to that the status is that the preset condition is not satisfied, determining that the test result is test failed, and outputting exception prompt information (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result is stored in the local flip-flop, so it is the Examiner’s interpretation that when the output fails to match the “golden signature,” the result indicating “fail” will be stored in the local flip-flop. “Exception prompt information” is broadly interpreted as any information that would indicate that there is an issue).
Per claim 16, Kamran in view of Hukerikar in further view of Dhonde teaches
The method according to claim 1, wherein the obtaining, by the processor core, an initialization instruction comprises:
detecting a trigger signal for entering a testing process; and (Kamran, page 258, “III. Test Timing” section, second paragraph, the execution of a local timer trigger indicates the start of the testing process)
obtaining the initialization instruction based on the trigger signal (Kamran, page 258, “III. Test Timing” section, second paragraph, after the trigger has been received, the test-snippet is executed. It is the Examiner’s interpretation that execution of the test-snippet will require obtaining the testing instructions).
Per claim 19, it recites similar claim limitation as claim 1. It further recites
A non-transient computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a processor testing method while being executed by a processor (Kamran, page 257, “II. Proposed Test Architecture” section, first paragraph, teaches many-core processor with a processing core, several cache blocks, and using the architecture for purposes of testing)
Per claim 20, it recites similar claim limitation as claim 1. It further recites
An electronic device, wherein the electronic device comprises: (Kamran, page 257, “II. Proposed Test Architecture” section, first paragraph, architecture)
a processor; and (Kamran, page 257, “II. Proposed Test Architecture” section, first paragraph, many-core processor)
a memory, configured to store processor-executable instructions, wherein the processor is configured to read the executable instruction from the memory, and execute the instruction to implement a processor testing method (Kamran, page 257, “II. Proposed Test Architecture” section, first paragraph, several cache blocks used for purposes of testing).
Claim(s) 2-4, 6-7, 10-12, 14-15, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja et al (US 11428737 B1).
Per claim 2, Kamran in view of Hukerikar in further view of Dhonde teaches
The method according to claim 1, wherein the controlling, by the processor core, the operation units to perform operation on the test input value, to obtain operation results comprises:
obtaining a … operation instruction and/or a … operation instruction; (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the local test controller (LTC) receives the test-snippet)
controlling, based on the ... operation instruction, a ... operation unit to perform operation on a ... input value in the test input value, to obtain a … operation result; (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the test-snippet is executed and the output is generated)
and controlling, based on the … operation instruction, a ... operation unit to perform operation on a ... input value in the test input value, to obtain a ... operation result, wherein the operation result comprises the ... operation result and/or the ... operation result. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the test-snippet is executed and the output is generated. Page 258, “E. Pass/Fail Circuit (PFC)” section, second column, combines multiple health status in order to determine the final result)
Kamran in view of Hukerikar in further view of Dhonde fails to teach explicitly
vector operation instruction and/or scalar operation instruction
vector operation unit to perform operation on a vector input value… to obtain a vector operation result
scalar operation unit to perform operation on a scalar input value… to obtain a scalar operation result
vector operation result and/or the scalar operation result
However, Ziaja teaches that the input data can include scalar inputs and vector inputs (col 17 lines 33-42) and the vector operation unit (col 3 lines 6-15, ALU may include SIMD, which is a vector operation unit) and scalar operation unit (col 3 lines 6-15, one or more ALU; furthermore, in col 17 lines 33-42 uses a scalar input which implies that the ALU can also be scalar)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kamran with the teachings of Ziaja because modern architecture contains both vector and scalar components and requires a more robust testing architecture that includes vector and scalar testing (Ziaja, col 4, lines 35-55). In Kamran, the art laid out the testing architecture without going into the specificity of whether the input included vector and scalar components. Ziaja filled that missing gap by detailing a more robust use case in which scalar and vector inputs are used during testing. Because by using scalar and vector inputs, the testing instruction would inherently become scalar and vector “operation instruction.” Furthermore, the corresponding result would inherently be scalar and vector “operation results” as well.
Per claim 3, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the determining, by the processor core, a test result based on the operation results comprising:
determining a first test result of the vector operation unit based on the vector operation result; (Ziaja, col 16 lines 46-col17 line 2 teaches that the array that is being tested may consist of subarrays with each comprising a set of BIST circuits for testing, with each their own BIST circuit controller. Furthermore, each of the subarray is individually testable as indicated in col 17. It is the Examiner’s interpretation that because this teaches subarrays that can be individually testable, and the testing inputs can be scalar or vector inputs as indicated in col 17 lines 33-42, one subarray can conduct scalar testing while the other conduct vector testing)
determining a second test result of the scalar operation unit based on the scalar operation result; and (see above)
determining the test result based on the first test result and the second test result. (Ziaja, col 16 lines 46-col 17 lines 2, a set of BIST circuits for testing is taught in which subarrays each with one or more processors can be tested individually. It yields predictable result to combine the result of these tests in order to get the overall result for the array)
Per claim 4, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the controlling, based on the vector operation instruction, a vector operation unit to perform operation on a vector input value in the test input value, to obtain a vector operation result comprises:
controlling, based on the vector operation instruction (Kamran, page 258, “D. Local Test Controllers (LTC)” section, execute the test-snippet), channels of the vector operation unit to respectively perform operation on the vector input value, to obtain operation results respectively corresponding to the channels; and (Ziaja, col 18, lines 57-65, the configurable unit includes ALU which may include a SIMD which supports multiple reconfigurable data channels)
the determining, by the processor core, a test result based on the operation result comprises:
determining a first test result of the vector operation unit based on the operation results respectively corresponding to the channels. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, determine the test result based on the result)
Per claim 6, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the determining, by the processor core, a test result based on the operation results comprising:
obtaining a scalar operation result of at least one other scalar operation unit, wherein the other scalar operation unit refers to an operation unit in another processor core except a current processor core where the scalar operation unit is located;
comparing the scalar operation result of the scalar operation unit with the scalar operation result of each other scalar operation unit to obtain a second comparison result; and
determining a second test result of the scalar operation unit based on the second comparison result. (Dhonde, col 10 lines 43-50, the operation result is obtained from an operation unit is compared against the result from a different test run. The comparison determines the overall test result; Ziaja, col 17 lines 33-42, the input may include scalar inputs; Ziaja, col 2 lines 60-65, the system includes two or more subarrays of processor units, each with its own testing circuit)
Per claim 7, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 6, wherein after the controlling, based on the scalar operation instruction, a scalar operation unit to perform operation on a scalar input value in the test input value, to obtain a scalar operation result, the method further comprises:
writing the scalar operation result into a shared storage space; and (Kamran, page 257, “E. Pass/Fail Circuit (PFC),” the result is reported to the CTC via a Pass/Fail Circuit)
the obtaining a scalar operation result of at least one other scalar operation unit comprises: (Dhonde, col 10 lines 43-50, teaches that comparing against every test run is a known substitution. It is the Examiner’s interpretation that in order to compare the value, it must be obtained first)
obtaining the scalar operation result of at least one other scalar operation unit from the shared storage space. (Dhonde, col 10 lines 43-50, teaches that comparing against every test run is a known substitution. It is the Examiner’s interpretation that in order to compare the value, it must be obtained first. In order for it to be obtained successfully, it must be stored in a shared storage space)
Per claim 10, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the obtaining, by the processor core, an initialization instruction comprises:
obtaining an immediate number initialization instruction, wherein the immediate number initialization instruction comprises the test input value to be written into the storage space. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, LTC receives a test-snippet and stores it in a local buffer and then executes the test-snippet. It is the Examiner’s interpretation that writing into the storage space is taught by this storing in the local buffer).
Per claim 11, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 3, wherein the obtaining, by the processor core, an initialization instruction comprises:
obtaining an immediate number initialization instruction, wherein the immediate number initialization instruction comprises the test input value to be written into the storage space. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, LTC receives a test-snippet and stores it in a local buffer and then executes the test-snippet. It is the Examiner’s interpretation that writing into the storage space is taught by this storing in the local buffer).
Per claim 12, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 4, wherein the obtaining, by the processor core, an initialization instruction comprises:
obtaining an immediate number initialization instruction, wherein the immediate number initialization instruction comprises the test input value to be written into the storage space. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, LTC receives a test-snippet and stores it in a local buffer and then executes the test-snippet. It is the Examiner’s interpretation that writing into the storage space is taught by this storing in the local buffer).
Per claim 14, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the determining, by the processor core, a test result based on the operation results comprising:
determining a status indicating whether or not the operation result satisfies a preset condition; (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the output is compared against the “golden signature”)
in response to that the status is that the preset condition is satisfied, determining that the test result is test succeeded; and (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result of the comparison is stored in the pass/fail result in a local flip-flop. It is the Examiner’s interpretation that if the output matches the “golden signature,” the result indicating “pass” will be stored in the local flip-flop).
in response to that the status is that the preset condition is not satisfied, determining that the test result is test failed, and outputting exception prompt information. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result is stored in the local flip-flop, so it is the Examiner’s interpretation that when the output fails to match the “golden signature,” the result indicating “fail” will be stored in the local flip-flop. “Exception prompt information” is broadly interpreted as any information that would indicate that there is an issue).
Per claim 15, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 3, wherein the determining, by the processor core, a test result based on the operation result comprising:
determining a status indicating whether or not the operation result satisfies a preset condition; (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the output is compared against the “golden signature”)
in response to that the status is that the preset condition is satisfied, determining that the test result is test succeeded; and (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result of the comparison is stored in the pass/fail result in a local flip-flop. It is the Examiner’s interpretation that if the output matches the “golden signature,” the result indicating “pass” will be stored in the local flip-flop).
in response to that the status is that the preset condition is not satisfied, determining that the test result is test failed, and outputting exception prompt information. (Kamran, page 258, “D. Local Test Controllers (LTC)” section, the result is stored in the local flip-flop, so it is the Examiner’s interpretation that when the output fails to match the “golden signature,” the result indicating “fail” will be stored in the local flip-flop. “Exception prompt information” is broadly interpreted as any information that would indicate that there is an issue).
Per claim 17, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 2, wherein the obtaining, by the processor core, an initialization instruction comprises:
detecting a trigger signal for entering a testing process; and (Kamran, page 258, “III. Test Timing” section, second paragraph, the execution of a local timer trigger indicates the start of the testing process)
obtaining the initialization instruction based on the trigger signal. (Kamran, page 258, “III. Test Timing” section, second paragraph, after the trigger has been received, the test-snippet is executed. It is the Examiner’s interpretation that execution of the test-snippet will require obtaining the testing instructions).
Per claim 18, Kamran in view of Hukerikar in further view of Dhonde in view of Ziaja teaches
The method according to claim 3, wherein the obtaining, by the processor core, an initialization instruction comprises:
detecting a trigger signal for entering a testing process; and (Kamran, page 258, “III. Test Timing” section, second paragraph, the execution of a local timer trigger indicates the start of the testing process)
obtaining the initialization instruction based on the trigger signal. (Kamran, page 258, “III. Test Timing” section, second paragraph, after the trigger has been received, the test-snippet is executed. It is the Examiner’s interpretation that execution of the test-snippet will require obtaining the testing instructions).
Allowable Subject Matter
Claim 5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites
wherein the determining a first test result of the vector operation unit based on the operation results respectively corresponding to the channels comprising:
for any one channel among the channels, taking the channel as a target channel, and comparing the operation result corresponding to the target channel with the operation result corresponding to at least one other channel among the channels except the target channel, to obtain a first comparison result corresponding to the target channel; and
determining a test result of the vector operation unit based on the first comparison result corresponding to each channel
Although Kamran in view of Ziaja does teach testing SIMD which supports multiple reconfigurable data channels (Ziaja, col 18 lines 56-65), it fails to teach the details in the claim limitation above. The Examiner was unable to find a prior art or an obvious combination of multiple prior art that would teach all the details in the claim limitation recited above.
Claim 8 recites
The method according to claim 7, wherein the obtaining the scalar operation result of at least one other scalar operation unit from the shared storage space comprises:
obtaining an acknowledgment signal indicating completion of writing back, wherein the acknowledgment signal is used to indicate that all scalar operation results of scalar operation units in processor cores have been written into the shared storage space, and the processor cores comprise the current processor core and other processor cores; and
obtaining the scalar operation result of the at least one other scalar operation unit from the shared storage space based on the acknowledgment signal.
Although Kamran teaches the test response being verified at the end of each test-cycle in order to detect faulty processing core (page 257, “II. Proposed Test Architecture” section), it fails to teach all of the details in the claim limitation recited above. The Examiner was unable to find a prior art or an obvious combination of multiple prior art to teach this.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.L.R./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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