The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 5/11/2026.
Claims 6-9 and 14-18 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Response to Arguments
Applicant`s arguments filed May 11, 2026 have been fully considered and they are persuasive with respect to prior art rejection.
As per the 103 rejection of claims 1 and 11, Applicant argued Liu/Li fails to disclose or suggest the feature of " a physical network layer (PHY); a microcontroller for performing PHY level operations; a dynamic random access memory (DRAM) for storing information for the compute system; a memory controller (MC) for controlling the DRAM over PHY; and a set of compute instructions, that when executed by the computer processor, cause the computer processor to disable at least one of the plurality memory channels"; where applicant argued that nowhere in paragraphs 0026-0030 of Li is there any mention of a "physical network layer (PHY). Furthermore, Li does not disclose a memory channel that itself comprises "a microcontroller for controlling the memory channel." Accordingly, the rejection mischaracterizes the teachings of Li to provide limitations that are explicitly missing from Liu, and a prima facie case of obviousness had not been established. However, Li teaches, in Fig. 1, SoC 102 that comprises various on-chip components electrically coupled via SoC bus 120. The SoC 102 comprises one or more memory clients (e.g., central processing unit(s) (CPU) 106, graphics processing unit(s) (GPU), digital signal processor(s) (DSPs)), a static random access memory (SRAM) 108, read only memory (ROM) 110, a DRAM controller 114, a storage controller 112, a power controller 118, and DRAM power manager interconnected via SoC bus 120. The CPU 106 may support a high-level operating system (O/S) 122. As described below in more detail, the O/S 122 supports a kernel memory manager 124 configured to provide memory allocation steering (module 126) and memory monitoring (module 128), where the memory controller, bus interface 136 and DRAM 104 form the memory channel and SoC bus 120, SRAM 108 and Controller 112 are associated with another memory channel, since there is no clear definition of what the PHY layer actually is as it was not defined in the claims nor in the specification, to correspond to the claimed limitations “a physical network layer (PHY); a microcontroller for performing PHY level operations; a dynamic random access memory (DRAM) for storing information for the compute system; a memory controller (MC) for controlling the DRAM over PHY”
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9 and 14-18 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “secure persistent data store” claim 6, claims are rejected under 35 U.S.C 112(b) as it is a relative term that was not defined.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-18 and 20 are rejected under 35 U.S.C. 103(a) as being disclosed by Liu et al. (US PGPUB 2016/0054947 hereinafter referred to as Liu), and further in view of Li et al. (US PGPUB 2019/0065087 hereinafter referred to as Li).
As per independent claim 1, Liu discloses a compute system in a system on chip (SoC) comprising: a computer processor; a memory in communication with the computer processor, the memory comprising a plurality of memory channels [(Paragraphs 0018-0024; FIG.1) wherein Liu teaches where FIG. 1 is a block diagram illustrating a memory system according to an embodiment of the present invention. The memory system 100 may be part of a computer system. For example, the memory system 100 may be implemented in a portable device, such as a tablet, a smartphone, or a wearable device. The memory system 100 may include a memory control system 101 and a multi-channel memory device (e.g., a dynamic random access memory) 102. The memory control system 101 may include a memory access controlling circuit 103 and a mode controlling module 108, where the memory access controlling circuit 103 may include a plurality of memory controllers 104_1-104_K and a direct memory access (DMA) controller 106. The mode controlling module 108 may be implemented using dedicated hardware, or may be implemented using software or firmware running on a processor. In this embodiment, the multi-channel memory device 102 may have a plurality of memory areas 110_1-110_K accessed via a plurality of memory channels 109_1-109_K, respectively. The memory controllers 104_1-104_K may be configured to control data access (i.e., read and write) of the memory areas 110_1-110_K, respectively. Hence, the number of memory controllers 104_1-104_K may be equal to the number of memory areas 110_1-110_K, and may also be equal to the number of memory channels 109_1-109_K to correspond to the claimed limitation], a memory channel comprising: a dynamic random access memory (DRAM) for storing information for the compute system [(Paragraphs 0018-0024; FIG.1) wherein Liu teaches where FIG. 1 is a block diagram illustrating a memory system according to an embodiment of the present invention. The memory system 100 may be part of a computer system. For example, the memory system 100 may be implemented in a portable device, such as a tablet, a smartphone, or a wearable device. The memory system 100 may include a memory control system 101 and a multi-channel memory device (e.g., a dynamic random access memory) 102. The memory control system 101 may include a memory access controlling circuit 103 and a mode controlling module 108, where the memory access controlling circuit 103 may include a plurality of memory controllers 104_1-104_K and a direct memory access (DMA) controller 106. The mode controlling module 108 may be implemented using dedicated hardware, or may be implemented using software or firmware running on a processor. In this embodiment, the multi-channel memory device 102 may have a plurality of memory areas 110_1-110_K accessed via a plurality of memory channels 109_1-109_K, respectively. The memory controllers 104_1-104_K may be configured to control data access (i.e., read and write) of the memory areas 110_1-110_K, respectively. Hence, the number of memory controllers 104_1-104_K may be equal to the number of memory areas 110_1-110_K, and may also be equal to the number of memory channels 109_1-109_K to correspond to the claimed limitation]; and a set of compute instructions, that when executed by the computer processor, cause the computer processor to disable at least one of the plurality memory channels [(Paragraphs 0018-0024 and 0032-0038; FIG.3) wherein Liu teaches where FIG. 3 is a diagram illustrating an example of managing the multi-channel memory device 102 according to a second embodiment of the present invention. As shown in FIG. 3, the multi-channel memory device 102 may include four memory areas 110_1-110_K (K=4) that may be accessed via four memory channels 109_1-109_K (K=4). When the multi-channel memory device 102 is controlled to operate under an M-channel mode (e.g., dual-channel mode with M=2), the memory areas 110_1-110_2 and the associated memory channels 109_1-109_2 may be active, while the memory areas 110_3-110_4 and the associated memory channels 109_3-109_4 may be disabled (e.g. powered down) or may enter the power-saving mode (e.g., self-refresh mode or other operation mode with power consumption lower than the normal mode). That is, the multi-channel memory device 102 may be partially active under the M-channel mode (e.g., dual-channel mode with M=2). When the multi-channel memory device 102 is controlled to operate under an N-channel mode (e.g., quad-channel mode with N=K=4=2×M), the memory areas 110_1-110_4 and the associated memory channels 109_1-109_4 may be active. That is, the multi-channel memory device 102 may be fully active under the N-channel mode (e.g., quad-channel mode with N=K=4=2×M) to correspond to the claimed limitation].
Liu does not appear to explicitly disclose a memory channel comprising: a physical network layer (PHY); a microcontroller for performing PHY level operations; a memory controller (MC) for controlling the DRAM over PHY.
However, Li discloses a memory channel comprising: a physical network layer (PHY); a microcontroller for performing PHY level operations; a memory controller (MC) for controlling the DRAM over PHY [(Paragraphs 0026-0030; FIGs. 1 and 6) where Li teaches a system 100 for memory power saving using kernel steering to one or more memory balloons. The system 100 comprises a system on chip (SoC) 102 electrically coupled to a volatile memory. In the embodiment of FIG. 1, the volatile memory comprises a dynamic random access memory (DRAM) 104 electrically coupled to the SoC 102 via a double data rate (DDR) interface 138. DRAM 104 may comprise one or more DRAM chips with each chip having a plurality of banks (e.g., 8 banks per DRAM chip). The system 100 provides an energy efficient method for controlling memory allocations to DRAM 104 from memory clients. The system 100 steers memory allocations to predetermined regions of the memory address space via memory ballooning. The data stored in one or more memory balloons (referred to as “power saving memory balloons”) may be migrated away from the associated balloon in DRAM 104, and processes associated with the balloons may be killed. Then, the memory sections corresponding to the balloons may be powered down to save memory power; in Fig. 1, SoC 102 that comprises various on-chip components electrically coupled via SoC bus 120. The SoC 102 comprises one or more memory clients (e.g., central processing unit(s) (CPU) 106, graphics processing unit(s) (GPU), digital signal processor(s) (DSPs)), a static random access memory (SRAM) 108, read only memory (ROM) 110, a DRAM controller 114, a storage controller 112, a power controller 118, and DRAM power manager interconnected via SoC bus 120. The CPU 106 may support a high-level operating system (O/S) 122. As described below in more detail, the O/S 122 supports a kernel memory manager 124 configured to provide memory allocation steering (module 126) and memory monitoring (module 128), where the memory controller, bus interface 136 and DRAM 104 form the memory channel and SoC bus 120, SRAM 108 and Controller 112 are associated with another memory channel to correspond to the claimed limitation].
Liu and Li are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Liu and Li before him or her, to modify the method of Liu to include the power saving operations of Li because it will enhance system performance.
The motivation for doing so would be [“ for improved systems and methods for efficiently reducing DRAM power” (Paragraph 0003 by Li)].
Therefore, it would have been obvious to combine Liu and Li to obtain the invention as specified in the instant claim.
As per dependent claim 2, Liu discloses four memory channels [(Paragraphs 0018-0024 and 0032-0038; FIGs.2 and 3) wherein Liu teaches where FIG. 2 is a diagram illustrating an example of managing the multi-channel memory device 102 according to a first embodiment of the present invention. As shown in FIG. 2, the multi-channel memory device 102 may include four memory areas 110_1-110_K (K=4) that may be accessed via four memory channels 109_1-109_K (K=4). When the multi-channel memory device 102 is controlled to operate under an M-channel mode (e.g., dual-channel mode with M=2), the memory areas 110_1-110_2 and the associated memory channels 109_1-109_2 may be active, while the memory areas 110_3-110_4 and the associated memory channels 109_3-109_4 may be disabled (e.g. powered down) or may enter the power-saving mode (e.g., self-refresh mode or other operation mode with power consumption lower than the normal mode). That is, the multi-channel memory device 102 may be partially active under the M-channel mode (i.e., dual-channel mode with M=2). When the multi-channel memory device 102 is controlled to operate under an N-channel mode (e.g., quad-channel mode with N=K=4=2×M), the memory areas 110_1-110_4 and the associated memory channels 109_1-109_4 may be active. That is, the multi-channel memory device 102 may be fully active under the N-channel mode (e.g., quad-channel mode with N=K=4=2×M) to correspond to the claimed limitation].
As per dependent claim 3, Li discloses compute instructions that, when executed by the computer processor, cause the processor to receive from a user a request to enter a power save mode of the compute system [(Paragraphs 0024-0028 and 0030-0034) wherein the memory power saving mode may be initiated in various ways. In one example, the memory power saving mode may be triggered via user interface 302 (FIG. 3) (e.g., a user command, a user-specified condition, etc.). A user may manually trigger the memory power saving mode via a user interface component. In other embodiments, the memory power saving mode may be triggered based on a user-specified remaining battery threshold, a user-specified schedule, etc. Furthermore, it should be appreciated that the user interface 302 may be used to define various user preference(s) indicating one or more user-installed applications, priority schedule(s), etc. that may be suspended or terminated. The kernel memory manager 124 may access the user preferences and use this information to steer memory allocations, configure memory balloon(s), or otherwise assist the kernel in cleaning up memory from the physical DRAM locations to be powered down. For example, when evaluating energy needed to inflate a balloon (i.e., power down the memory range) to correspond to the claimed limitation].
As per dependent claim 4, Li discloses an indicator representative of a number of memory channels, of the plurality of memory channels, to disable [(Paragraphs 0032; FIGs. 1 and 5) where Li teaches user may manually trigger the memory power saving mode via a user interface component. In other embodiments, the memory power saving mode may be triggered based on a user-specified remaining battery threshold, a user-specified schedule, etc. Furthermore, it should be appreciated that the user interface 302 may be used to define various user preference(s) indicating one or more user-installed applications, priority schedule(s), etc. that may be suspended or terminated. The kernel memory manager 124 may access the user preferences and use this information to steer memory allocations, configure memory balloon(s), or otherwise assist the kernel in cleaning up memory from the physical DRAM locations to be powered down. For example, when evaluating energy needed to inflate a balloon (i.e., power down the memory range), the kernel may gather a list of user processes associated with active pages in the balloon physical address range. The kernel may check user preference(s) to decide whether to terminate a specific user application so that the pages associated with the user application can be freed. In this manner, the energy required to perform page migration upon entering power saving mode may be reduced. Furthermore, it should be appreciated that a system initialization process may provide the memory topology to the HLOS kernel (e.g., the number of banks, bank sizes, number of ranks, number of channels, interlevel configuration, the manner in which the HLOS physical address is mapped to the DRAM memory topology, etc.). Any of this information may be used to determine a number, size, and location of the memory balloons to correspond to the claimed limitation].
As per dependent claim 5, Li discloses a set of compute instructions that when executed by the computer processor cause the computer processor to power gate the indicated number of memory channels to isolate power therefrom [(Paragraphs 0032; FIGs. 1 and 5) where Li teaches user may manually trigger the memory power saving mode via a user interface component. In other embodiments, the memory power saving mode may be triggered based on a user-specified remaining battery threshold, a user-specified schedule, etc. Furthermore, it should be appreciated that the user interface 302 may be used to define various user preference(s) indicating one or more user-installed applications, priority schedule(s), etc. that may be suspended or terminated. The kernel memory manager 124 may access the user preferences and use this information to steer memory allocations, configure memory balloon(s), or otherwise assist the kernel in cleaning up memory from the physical DRAM locations to be powered down. For example, when evaluating energy needed to inflate a balloon (i.e., power down the memory range), the kernel may gather a list of user processes associated with active pages in the balloon physical address range. The kernel may check user preference(s) to decide whether to terminate a specific user application so that the pages associated with the user application can be freed. In this manner, the energy required to perform page migration upon entering power saving mode may be reduced. Furthermore, it should be appreciated that a system initialization process may provide the memory topology to the HLOS kernel (e.g., the number of banks, bank sizes, number of ranks, number of channels, interlevel configuration, the manner in which the HLOS physical address is mapped to the DRAM memory topology, etc.). Any of this information may be used to determine a number, size, and location of the memory balloons to correspond to the claimed limitation].
As per dependent claim 6, Li discloses a secure persistent data store for receiving data stored in the DRAMs during runtime of the compute system [(Paragraphs 0029-0033; FIGs. 1 and 5) where Li teaches power controller 118 is electrically coupled to a power supply 130 via a power control bus 134. The storage controller 112 may be electrically coupled via a storage bus 138 to external non-volatile storage memory, such as, for example, flash memory 132 or other non-volatile memory device(s). Storage controller 112 controls communication with the external storage memory. The DRAM controller 114 controls communication with DRAM 104. The power and DDR manager 116 communicates with the power controller 118 and the DRAM controller 114 via SoC bus 120. The power and DDR manager 116 may comprise software running on CPU 106, or a separate hardware block or subsystem in SoC 102; the data from at least one memory balloon may be cleaned up from the DRAM 104. FIG. 4 illustrates an example in which the data from memory balloon 306a is swapped (reference numeral 404) to a swap file 402 residing in flash 132. In this regard, the kernel may check the number of active pages in the balloon, and determine whether there is an unmovable page in the balloon. Referring to FIG. 4, balloon device 306b illustrates an example where there is an unmovable page in the balloon, and the number of active pages is above, for example, a configurable maximum threshold even after termination of a user application as described in previous paragraph. Then, the kernel may decide not to power down this balloon. In the exemplary balloon device 306a, the active pages may be below the maximum threshold, and there may be no unmovable pages, in which case the kennel may decide to power down this balloon. The kernel may initiate balloon inflation by allocating empty pages into the balloon to clean up the existing pages. In order to get memory for the empty pages allocation, the kernel may invoke various mechanisms (e.g., swapping pages to flash 132, dropping file cache, killing user applications, migrating/copying pages to non-power down balloons, etc.) to correspond to the claimed limitation].
As per dependent claim 7, Li discloses a set of compute instructions that when executed by the computer processor cause the computer processor, upon receiving the request from a user to enter the power saving mode, to perform a swap of memory from the DRAMs of the plurality of memory channels to the secure persistent data store [(Paragraphs 0029-0033; FIGs. 1 and 5) where Li teaches power controller 118 is electrically coupled to a power supply 130 via a power control bus 134. The storage controller 112 may be electrically coupled via a storage bus 138 to external non-volatile storage memory, such as, for example, flash memory 132 or other non-volatile memory device(s). Storage controller 112 controls communication with the external storage memory. The DRAM controller 114 controls communication with DRAM 104. The power and DDR manager 116 communicates with the power controller 118 and the DRAM controller 114 via SoC bus 120. The power and DDR manager 116 may comprise software running on CPU 106, or a separate hardware block or subsystem in SoC 102; the data from at least one memory balloon may be cleaned up from the DRAM 104. FIG. 4 illustrates an example in which the data from memory balloon 306a is swapped (reference numeral 404) to a swap file 402 residing in flash 132. In this regard, the kernel may check the number of active pages in the balloon, and determine whether there is an unmovable page in the balloon. Referring to FIG. 4, balloon device 306b illustrates an example where there is an unmovable page in the balloon, and the number of active pages is above, for example, a configurable maximum threshold even after termination of a user application as described in previous paragraph. Then, the kernel may decide not to power down this balloon. In the exemplary balloon device 306a, the active pages may be below the maximum threshold, and there may be no unmovable pages, in which case the kennel may decide to power down this balloon. The kernel may initiate balloon inflation by allocating empty pages into the balloon to clean up the existing pages. In order to get memory for the empty pages allocation, the kernel may invoke various mechanisms (e.g., swapping pages to flash 132, dropping file cache, killing user applications, migrating/copying pages to non-power down balloons, etc.) to correspond to the claimed limitation].
As per dependent claim 8, Liu discloses a set of compute instructions that when executed by the computer processor cause the computer processor to: transfer data from the DRAMs to the secure persistent data store; reconfigure the compute system memory based on the number of remaining active memory channels; and transfer the data from the secure persistent memory back into the DRAMs of the remaining active memory channels [(Paragraphs 0045-0049; FIGs. 1 and 6) where Liu teaches FIG. 6 is a diagram illustrating an example of managing a multi-channel memory device according to a fourth embodiment of the present invention. The only difference between the multi-channel memory management examples shown in FIG. 2 and FIG. 6 is the design of the reserved partial memory space allocation. In this embodiment shown in FIG. 6, when the multi-channel memory device 102 is controlled to operate in the M-channel mode (e.g., dual-channel mode with M=2), a partial memory space 602 (which may be across the memory channels 109_3-109_4 and may be composed of memory regions R2, R3, . . . , R70 and R71) may be reserved by the memory access controlling circuit 103. Since the partial memory space 602 may be reserved at the memory channels 109_3 and 109_4 that may be disabled (e.g. powered down) or may enter the power-saving mode (e.g., self-refresh mode or other operation mode with power consumption lower than the normal mode) under the M-channel mode (e.g., dual-channel mode with M=2), the partial memory space 602 may be blocked from being used under the M-channel mode (e.g., dual-channel mode with M=2). In addition, since the memory channels 109_3 and 109_4 may be enabled under the N-channel mode (e.g., quad-channel mode with N=4), the partial memory space 602 may be allowed to be used under the N-channel mode (e.g., quad-channel mode with N=4) to correspond to the claimed limitation].
As per dependent claim 9, Li discloses monitor operations of the compute system; and initiate swapping of data from DRAMs to secure persistent data store and back to remaining active DRAMs based on an operating state of the compute system [(Paragraphs 0031-0036 and 0041-0049; FIGs. 1 and 9) where Li teaches as shown in the method of FIG. 9. At step 900, during system run time, the memory monitor module 128 may wake up based on, for example, a tunable kernel parameter 814, and begin monitoring how much memory is being used on the system 100 (e.g., detect memory pressure condition(s)). At step 910, the memory monitor module 128 may check if the amount of free pages is below a threshold or the memory pressure is higher than a threshold specified in, for example, the configuration parameter 817. If the memory pressure is higher than the threshold, the system 100 may need to clean up some memory pages or power-on memory to reach this goal. At step 920, the memory monitor module 128 may check if there any user applications that may be killed to free up the memory to reach the goal. It should be appreciated that the target application(s) to be killed may have a “kill preference” higher than the configuration item 812 when user installed or configured by the application. At step 921, the memory monitor module 128 may identify victim application(s), and then proceed with the application killing process. As illustrated at step 922, the memory monitor module 128 may be unable to recover enough memory to reach the goal, and then initiate the process to power on memory to correspond to the claimed limitation].
As per dependent claim 18, Li discloses monitor operations of the compute system; and initiate swapping of data from DRAMs to secure persistent data store and back to remaining active DRAMs based on an operating state of the compute system [(Paragraphs 0040-0049; FIGs. 1 and 9) where Li teaches where the memory monitor module 128 may be configured to access various policy knob settings (e.g., configuration parameters 810 in FIG. 8a) and, in response, schedule a work item to perform various “active” actions. Following is a description of various exemplary “active” actions, as shown in the method of FIG. 9. At step 900, during system run time, the memory monitor module 128 may wake up based on, for example, a tunable kernel parameter 814, and begin monitoring how much memory is being used on the system 100 (e.g., detect memory pressure condition(s)). At step 910, the memory monitor module 128 may check if the amount of free pages is below a threshold or the memory pressure is higher than a threshold specified in, for example, the configuration parameter 817. If the memory pressure is higher than the threshold, the system 100 may need to clean up some memory pages or power-on memory to reach this goal. At step 920, the memory monitor module 128 may check if there any user applications that may be killed to free up the memory to reach the goal. It should be appreciated that the target application(s) to be killed may have a “kill preference” higher than the configuration item 812 when user installed or configured by the application. At step 921, the memory monitor module 128 may identify victim application(s), and then proceed with the application killing process. As illustrated at step 922, the memory monitor module 128 may be unable to recover enough memory to reach the goal, and then initiate the process to power on memory
to correspond to the claimed limitation].
As for independent claim 11, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 12, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claim 13, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
As for dependent claim 14, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
As for dependent claim 15, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
As for dependent claim 16, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
As for dependent claim 17, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
As for dependent claim 20, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
Claims 10 and 19 is rejected under 35 U.S.C. 103(a) as being disclosed by Liu and Li, as applied to claims 1 and 11, and further in view of Samuel et al. (US PGPUB 2024/0078158 hereinafter referred to as Samuel).
As per dependent claim 10, Liu/Li discloses the system of claim 1.
Liu/Li does not appear to explicitly disclose detect a hardware failure in at least one of the plurality of memory channels; and initiate a power saving mode during runtime to disable the memory channel where a hardware failure has been detected.
However, Samuel discloses detect a hardware failure in at least one of the plurality of memory channels; and initiate a power saving mode during runtime to disable the memory channel where a hardware failure has been detected [(Paragraphs 0060-0062 and 0073; Figs.4 and 6 and their related text) wherein BIOS 207 sets IHS 200 in mitigation mode, for example, by excluding or disabling one or more slots and/or memory channels to which the failed DIMM is connected. This mitigation mode allows IHS 200 to continue to boot—albeit with reduced memory. Still at 402, BIOS 207 may set the “mitigation flag” in the NVRAM; BIOS 207 sets IHS 200 in mitigation mode, for example, by excluding or disabling one or more slots and/or memory channels to which the failed DIMM is connected. This mitigation mode allows IHS 200 to continue to boot—albeit with reduced memory. Still at 402, BIOS 207 may set the “mitigation flag” in the NVRAM; while the new memory is in transit (e.g., from a warehouse to the user) IHS 200 operates with low memory and potential performance issues—i.e., still in mitigation mode. At 406, however, the user receives the replacement DIMM. At 407, the failed memory is replaced with the new memory, which triggers chassis intrusion event 408 (e.g., activation of a switch). In response to event 408 and request 410, at 409 method 400 returns IHS 200 to normal mode by re-booting and starting the BIOS's memory initialization processes, such that all installed DIMMs and memory channels are enabled, and the “mitigation mode” flag is cleared in the NVRAM to correspond to the claimed limitation].
Liu/Li and Samuel are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Liu/Li and Samuel before him or her, to modify the method of Liu/Li to include the mitigation operations of Samuel because it will enhance system performance.
The motivation for doing so would be [“automatically mitigate the failure (e.g., by disabling a defective channel) and continue its booting process with reduced memory capabilities” (Paragraph 0004 by Samuel)].
Therefore, it would have been obvious to combine Liu/Li and Samuel to obtain the invention as specified in the instant claim.
As for dependent claims 19, the applicant is directed to the rejections to claim 10 set forth above, as they are rejected based on the same rationale.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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