DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 05/07/2026. Claims 1, 6, 8, 13, 15, and 19 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a provisional application, 63/626691 filed on 01/30/2024, is acknowledged.
Response to Amendments and Arguments
Applicant Amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10, and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. (US 2022/0375525), hereinafter Iwasaki in view of Shridhar et al. (US2022/0300194), hereinafter Shridhar, and further in view of Baruch et al. (US2025/0123970), hereinafter Baruch and Liu et al. (US2020/0371710), hereinafter Liu.
Regarding claims 1, 8, and 15, taking claim 1 as exemplary, Iwasaki teaches a memory device comprising:
a memory array (Iwasaki, [0035], Each of the memory devices 130 can include one or more arrays of memory cells);
a page buffer (Iwasaki, [0051], a page buffer of the memory device 130); and
control logic (Iwasaki, [0042], which includes a raw memory device 130 having control logic (e.g., local media controller 135) on the die ), operatively coupled to the memory array and the page buffer, to perform operations comprising:
receiving, from a memory sub-system controller, a command related to execution of a memory access operation associated with one or more memory blocks of the memory array of the memory device (Iwasaki, [0040], The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130; [0043]);
receiving, from the memory sub-system controller in connection with the memory access operation, a second command indicating that a portion of the page buffer is to be reserved
in response to the second command, reserving the portion of the page buffer; and
causing at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer.
Iwasaki does not explicitly teach receiving, from the memory sub-system controller in connection with the memory access operation, a second command indicating that a portion of the page buffer is to be reserved; in response to the second command, reserving the portion of the page buffer; and causing at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer, as claimed.
However, Iwasaki in view of Shridhar teaches receiving, from the memory sub-system controller in connection with the memory access operation, a second command indicating that a portion of the page buffer is to be reserved (Shridhar, [0019], This is achieved by allocating commands to specific NAND page buffers via NAND page buffer identifiers and a NAND page buffer status table, for example. This allows the controller to control which NAND page buffers are used).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwasaki to incorporate teachings of Shridhar to include a command that is issued from a controller to a memory device and is specifically used to allocate a portion of page buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Shridhar because it improves efficiency and flexibility of the storage system disclosed in the combination of Iwasaki by allowing a memory controller to flexibly manage page buffer.
The combination of Iwasaki does not explicitly teach in response to the second command, reserving the portion of the page buffer; and causing at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer, as claimed.
However, the combination of Iwasaki in view of Baruch teaches receiving, from the memory sub-system controller in connection with the memory access operation, a second command indicating that a portion of the page buffer is to be reserved (Shridhar, [0019]; Baruch, [0064], flush ownership process 10 allocates 404 a set of page buffers to a first mapping page when ingesting or processing an IO request … flush ownership process 10 allocates a set of page buffers (e.g., page buffers 504, 506, 508) to a first mapping page (e.g., mapping page 520)).
in response to the second command, reserving the portion of the page buffer (Baruch, [0066], flush ownership process 10 uses the logical address of the IO request to allocate the PLB or page buffer to a particular mapping page); and
causing at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer (Baruch, [0068], flush ownership process 10 may flush 410 data from mapping page 520 by flushing page buffers 504, 506, 508 to storage array 112).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwasaki to incorporate teachings of Baruch to allocate and reserve page buffer for non-host data such as mapping data and store the mapping data in the allocated page buffer in according to a command. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Baruch because it improves reliability of the storage system disclosed in the combination of Iwasaki by providing persistent memory storage for storing mapping data.
The combination of Iwasaki does not explicitly teach non-host data received from a high-performance local memory of the memory sub-system controller, as claimed.
However, the combination of Iwasaki in view of Liu teaches causing at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller (Liu, [0030], In addition, the metadata stored at the memory array 41 a (MAa1) and the metadata stored at the memory array 41 b (MAa2) are copied to the sub-mapping circuits 235 a, 235 b, respectively … the mapping circuit 235 can be implemented with an SDRAM ) to be stored in the portion of the page buffer (Liu, [0031], flush cache; [0043]; [0081], the write metadata generated by the control logic 631 are recorded at the memory array 6331 through the use of the page buffer 6347).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwasaki to incorporate teachings of Liu to include a SDRAM buffer in memory sub-system controller 115 (of Iwasaki) to store mapping data/metadata, assign a portion of a page buffer to the mapping data in response to an allocation command, and transmit the mapping data stored in the SDRAM buffer to the allocated area of the page buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Liu because it improves performance of the storage system disclosed in the combination of Iwasaki by accessing mapping data from a SDRAM buffer memory.
Claims 8 and 15 have similar limitations as claim 1 and they are rejected for the similar reasons.
Regarding claims 2 and 9, taking claim 2 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 1 as outlined above. The combination of Iwasaki further teaches the memory device of claim 1, wherein the memory access operation is associated with one or more single level cell (SLC) blocks of the memory device (Iwasaki, [0025], While the examples described herein involve single level cell (SLC) programming).
Claim 9 has similar limitations as claim 2 and is rejected for the similar reasons.
Regarding claims 3 and 10, taking claim 3 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 2 as outlined above. The combination of Iwasaki further teaches the memory device of claim 2, wherein the memory access operation comprises one of an SLC read operation, an SLC program operation, or an SLC erase operation (Iwasaki, [0043], such as program commands, read commands, or other commands; Shridhar, [0008], the memory storage system comprises single-level memory cells (SLCs); [0017], d SSD program/write and read commands).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwasaki to incorporate teachings of Shridhar to include SLC memory mode for I/O commands. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Shridhar because it improves efficiency and flexibility of the storage system disclosed in the combination of Iwasaki by allowing a memory controller to flexibly manage page buffer.
Claim 10 has similar limitations as claim 3 and is rejected for the similar reasons.
Regarding claim 16, the claim is rejected for the same reasons set forth with respect to claims 2 and 3, as claim 16 recites limitations that are similar to those recited in claims 2 and 3.
Claim(s) 4, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Iwasaki, Shridhar, Baruch, and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Lee et al. (US 2023/0400992), hereinafter Lee and Yang et al. (US 2015/0339195), hereinafter Yang.
Regarding claims 4, 11, and 17, taking claim 4 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 1 as outlined above. The combination of Iwasaki does not explicitly teach the memory device of claim 1, wherein the non-host data comprises one or more of firmware variables or firmware code, as claimed.
However, the combination of Iwasaki in view of Lee and Yang teaches the memory device of claim 1, wherein the non-host data comprises one or more of firmware variables or firmware code (Lee, [0079], the setting data CDATA are general setting data, and may include setting data for at least one of the SLC erase, the SLC program, the SLC read; [0118], the setting operation IDR_A may be performed to the chip to which the main firmware code is programmed. The setting operation IDR_A for the SLC read may include a sensing for reading the setting data CDATA needed for the SLC read from the first region 111 and storing the same in the page buffer 140; Yang, [0033], Memory system 212 may receive the boot code and configuration parameters into RAM 218).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwasaki to incorporate teachings of Lee and Yang to allocate a spare area of a page buffer in response to a SLC access command and transmit SLC setting data stored in a RAM memory of a storage controller to the spare area of the page buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of Iwasaki with Lee and Yang because it improves efficiency and reliability of the storage system disclosed in Iwasaki by providing configuration data for a memory array in order to process incoming I/O commands.
Claims 11 and 17 have similar limitations as claim 4 and they are rejected for the similar reasons.
Claim(s) 5, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Iwasaki, Shridhar, Baruch, and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Han (US 2025/0140327), hereinafter Han.
Regarding claims 5, 12, and 18, taking claim 5 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 1 as outlined above. The combination of Iwasaki does not explicitly teach the memory device of claim 1, wherein the portion of the page buffer reserved to store the non-host data comprises one or more data latch circuits of the page buffer, as claimed.
However, the combination of Iwasaki in view of Han teaches the memory device of claim 1, wherein the portion of the page buffer reserved to store the non-host data comprises one or more data latch circuits of the page buffer (Han, [0021], page buffer 204 may include … (N-1) data latches (D1 to DN-1) (e.g., a first data latch (D1) 3333 and a second data latch (D2) 3335)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwasaki to incorporate teachings of Han to include data latches in a page buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Han because it improves reliability of the storage system disclosed in the combination of Iwasaki by holding data stable in a data latch of a page buffer.
Claims 12 and 18 have similar limitations as claim 5 and they are rejected for the similar reasons.
Claim(s) 6, 13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Iwasaki, Shridhar, Baruch, and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Lee et al. (US 2023/0400992), hereinafter Lee.
Regarding claims 6, 13, and 19, taking claim 6 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 1 as outlined above. The combination of Iwasaki does not explicitly teach the memory device of claim 1, wherein the command comprises one of a Set Feature command, a prefix command, or a trim option, as claimed.
However, the combination of Iwasaki in view of Lee teaches the memory device of claim 1, wherein the second command comprises one of a Set Feature command (Lee, [0086], a set-feature-type command sequence CMDs for different initializing and setting operations may be found), a prefix command, or a trim option.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwasaki to incorporate teachings of Lee to include a set-feature type command to initialize and set a memory device for memory access operations. A person of ordinary skill in the art would have been motivated to combine the teachings of Iwasaki with Lee and Yang because it improves efficiency and reliability of the storage system disclosed in Iwasaki by providing configuration data for a memory array in order to process incoming I/O commands.
Claims 13 and 19 have similar limitations as claim 6 and they are rejected for the similar reasons.
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Iwasaki, Shridhar, Baruch, and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Lee et al. (US 2023/0400992), hereinafter Lee and Choi et al. (US2017/0038969), hereinafter Choi.
Regarding claims 7, 14, and 20, taking claim 7 as exemplary, the combination of Iwasaki teaches all the features with respect to claim 1 as outlined above. The combination of Iwasaki does not explicitly teach the memory device of claim 1, wherein following causing the non-host data to be stored in the portion of the page buffer, additional host data is caused to be stored in the high- performance local memory of the memory sub-system controller, as claimed.
However, the combination of Iwasaki in view of Lee and Choi teaches the memory device of claim 1, wherein following causing the non-host data to be stored in the portion of the page buffer, additional host data is caused to be stored in the high- performance local memory of the memory sub-system controller (Lee, [0050], may perform a setting operation of the memory device 100 for operations that are needed by priority by using the setting data CDATA … SLC program; [0051], The setting operation includes a sensing for reading the setting data CDATA of the first region 111 to the page buffer 140; Choi, [0051], At step S131, the controller 100 may control the mode setting operation of the nonvolatile memory device 200 such that a write mode is set to the SLC mode; [0052], the controller 100 may control the mode setting operation before controlling the buffer write operation of the nonvolatile memory device 200 at step S132; [0057], At step S132, the controller 100 may control the buffer write operation of the nonvolatile memory device 200 such that the write-requested data is stored in the buffer region 210; [0061], When it is determined at step S134 that remaining data exists but it is not a data overflow state (“Y, N” of step S134), the process may proceed to step S132. At step S132, the controller 100 may control the buffer write operation of the nonvolatile memory device 200 such that remaining data is stored in the buffer region 210).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwasaki to incorporate teachings of Lee and Choi to store additional write data to a write buffer after a write mode (such as SLC) is set. As such, the write data is transmitted to a nonvolatile storage device from the write buffer and stored in accordance with the set mode. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Iwasaki with Lee and Choi because it improves efficiency of the storage system disclosed in the combination of Iwasaki by temporarily store write data in a write buffer before programming the write data into a nonvolatile storage device in order to reduce write amplification.
Claims 14 and 20 have similar limitations as claim 7 and they are rejected for the similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fujiwara et al. (US 2014/0089768) teaches storing parity data in a selected portion of a page buffer ([0063].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137
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