DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to rejected claim(s) have been considered but are moot in view of the new ground of rejection below.
Applicant argues that Fujiwara does not disclose debug operations "configured to collect system state information relating to operation of the memory device", as recited in amended claim 1 because Fujiwara's fail bit map is not "system state information relating to operation of the memory device." Fujiwara teaches a fail bit counter (Fig. 7, 105) “which counts the number of fail bits on the SRAM.” The specification at paragraph 15 provides an example of system state information being “a warning related to some reliability statistic (e.g., raw bit error rate (RBER)) of a memory device, [or] an error experienced by the memory sub-system controller in reading data from or writing data to a memory device, etc”. The Examiner asserts that anyone skilled in the art at the time the invention was filed would have recognized that the fail bit count of Fujiwara is an example of system state information according to the definition above.
Applicant argues that Fujiwara does not disclose executing debug operations "during runtime of the memory device," as recited in amended claim 1. The Examiner notes that Chakravarty is relied upon to address this limitation in the new grounds of rejection below.
Applicant argues that Fujiwara does not disclose "providing debug results generated based on the system state information to the memory sub-system controller," as recited in amended claim 1 because Fujiwara’s fail bit map differs from providing debug results based on system state information. As noted above, the rejection does not rely on Fujiwara’s fail bit map. Fujiwara additionally teaches a fail bit count, and providing results based on this count as shown in Fig. 27, S1207.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 7-9, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al (US Pat. 8,659,969; hereinafter referred to as Fujiawara) in view of Chakravarty et al (US Pat. Pub. 2023/0084463; hereinafter referred to as Chakravarty).
As per claim 1: Fujiwara teaches a memory device comprising:
a memory array (Fig. 7, 103a); and
control logic, operatively coupled to the memory array (Fig. 7, 201), to perform operations comprising:
receiving, from a memory sub-system controller (Fig. 7, 101 and 104), a command related to a sequence of one or more debug operations associated with the memory device (col. 5, line 56), wherein the one or more debug operations are configured to collect system state information relating to operation of the memory device (Fig. 7, 105);
in response to the command, executing the sequence of the one or more debug operations to collect the system state information (col. 6, lines 34-35; Fig. 27, S1205-S1206); and
providing debug results generated based on the system state information to the memory sub-system controller (col. 5, line 57; Fig. 27, S1207).
Not explicitly disclosed is collecting the system state information during runtime of the memory device. However, Chakravarty in an analogous art teaches debug operations executed during runtime associated with a memory device (paragraph 17).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to execute the debug of Fujiwara during memory runtime. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed detection of errors during runtime without requiring the system to be brought down (paragraph 17).
As per claims 2, 9, 16:
Fujiwara teaches the memory device of claim 1, method of claim 8, and storage medium of claim 15 wherein the command comprises address information identifying at least a portion of the memory device (col. 6, lines 46-48).As per claims 7, 14: Fujiwara teaches the memory device of claim 1 and method of claim 8 above. Not explicitly disclosed is wherein the debug results comprise confirmation of execution of the one or more debug operations associated with the memory device. However, Chakravarty in an analogous art teaches a debug execution command (Fig. 3A, request command rta_bist_req) and a confirmation of execution (Fig. 3A, grant command rta_bist_gnt; paragraph 26).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to include a confirmation of execution in Fujiwara. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was a matter of design choice that would have produced expected results without changing the principal of operation.
As per claims 8, 15: Fujiwara teaches a method and non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving, by a processing device (Fig. 7, 104) from a memory sub-system controller (Fig. 7, 101), a command related to a sequence of one or more debug operations (col. 5, line 56) associated with a memory device (Fig. 7, 103a), wherein the one or more debug operations are configured to collect system state information relating to operation of the memory device (Fig. 7, 105);
in response to the command, executing, by the processing device, the sequence of the one or more debug operations to collect the system state information (col. 6, lines 34-35; Fig. 27, S1205-S1206); and
providing, by the processing device, debug results generated based on the system state information to the memory sub-system controller (col. 5, line 57; Fig. 27, S1207).
Not explicitly disclosed is collecting the system state information during runtime of the memory device. However, Chakravarty in an analogous art teaches debug operations executed during runtime associated with a memory device (paragraph 17).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to execute the debug of Fujiwara during memory runtime. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed detection of errors during runtime without requiring the system to be brought down (paragraph 17).
Claim(s) 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Chakravarty in view of Ong (US Pat. 7,313,740).
As per claims 3, 10, 17:
Fujiwara teaches the memory device of claim 1, method of claim 8, and storage medium of claim 15 above. Not explicitly disclosed is wherein the sequence of the one or more debug operations comprises one or more of a read offset data collection operation, a loading of data from the memory sub-system controller to the memory device, or an algorithm debug operation. However, Ong in an analogous art teaches an onboard test pattern generator (Fig. 2, 230).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a test pattern generator in the system of Fujiwara. This modification would have been obvious for one of ordinary skill in the art at the time of filing because writing data to test the memory was required by Fujiwara (col. 6, lines 46-48), and Ong teaches a known means to accomplish that.
Claim(s) 6, 13, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Chakravarty in view of Papandreou et al (US Pat. Pub. 2021/0065813; hereinafter referred to as Papandreou).
As per claims 6, 13, 20: Fujiwara teaches the memory device of claim 1, method of claim 8, and storage medium of claim 15 above. Not explicitly disclosed is wherein the debug results comprise read offset data relating to one or more wordlines of the memory device. However, Papandreou in an analogous art teaches read offset data relating to one or more wordlines of the memory device (Fig. 8, 800).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the read offset calibration table 800 of Papandreou in the memory for Fujiwara et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because calibration has been shown to significantly improve the RBER and therefore enhance endurance and retention (paragraph 4).
Claim(s) 5, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Chakravarty in view of Weksler et al (US Pat. Pub. 2015/0279485; hereinafter referred to as Weksler).
As per claims 5, 12, 19: Fujiwara teaches the memory device of claim 1, method of claim 8, and storage medium of claim 15 above. Not explicitly disclosed is wherein the command comprises an instruction to pause one or more in-progress operations associated with the memory device. However, Weksler in an analogous art teaches sending an interrupt to pause in-progress operations associated with a memory during testing (paragraph 63).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to implement an interrupt signal to pause operations as taught by Weksler. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed memory testing during operation, as shown by Weksler.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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