Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6 and 14 of U.S. Patent No. 12,242,735.
Claim(s) 6 and 14 of patent # 12,242,735 contain(s) every element of claim(s) 1 and 11 of the instant application and as such anticipate(s) claim(s) 1 and 11 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example claim mapping between the instant application and patent:
Instant Application
A memory system, comprising:
a memory device including at least one memory die including memory planes, wherein the at least one memory die includes code blocks storing code data, the code data stored in the code blocks are identical, and the code blocks are disposed in different memory planes; and
a memory controller coupled to the memory device and configured to: read a portion of the code data from each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation; and
combine the portion of the code data read from each code block of the at least the
portion of code blocks into complete code
data according to a preset rule.
Patent 12,242,735
1.A memory system, comprising:
a memory device including at least one memory die, and the memory die includes a plurality of code blocks, wherein a number of the plurality of code blocks is M and each of the code blocks includes N code pages, wherein M and N are positive integers greater than 1, and the plurality of code blocks store identical code data, and wherein the memory die includes a plurality of memory planes, and the plurality of code blocks are stored in different memory planes; and
a memory controller coupled to the memory device, wherein the memory controller is configured to at least read a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation, wherein a read portion of code data of each code block constitutes complete code data stored in one code block, wherein to read the portion of code data of each code block further includes: if M is equal to N, read code data of one code page of each of the code blocks simultaneously according to a first preset rule; if M is greater than N, read code data of one code page of each of the code blocks of N code blocks simultaneously according to a second preset rule; and if M is less than N, for a first to an i-th times, read the code data of one code page of each of the code blocks simultaneously each time according to a third preset rule, and, for an i+1-th time, read code data of one code page of each of the code blocks of j code blocks simultaneously, wherein (i+1) is a quotient of N divided by M, and j is a remainder of N divided by M, wherein the code data read from each of the code pages is different.
The memory system according to claim 1, wherein the memory controller is configured to: after reading the portion of code data of each code block of at least the portion of code blocks simultaneously,
combine the read portion of code data of each code block into the complete code data stored in one code block according to a preset rule; and perform related operations after power-on or related operations of exiting a low power consumption mode using the complete code data.
As can be seen above, claim 7 (incorporating claim 1) of the patent includes all of the limitations claim 1 of the instant application, anticipating claim 1 of the instant application.
Claim 14 (incorporating claim 10) of the patent similarly anticipates claim 11 of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 7-11, 14, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravimohan et al (US20160077749, “Ravimohan”, in view of Liang (US20210200633).
As to claim 1, 20:
Ravimohan teaches a memory system (multi-plane memory system; Fig. 1; 0010-0012), an apparatus comprising a memory controller (flash memory including memory array and controller; Fig .1, 0040-0042), comprising:
a memory device comprising at least one memory die (solid-state memory device having memory dies; Fig. 4-5; 0002, 0009, 0046-0047), and the memory die comprises a plurality of code blocks storing a code (block storing boot code; 0010, 0012, 0052, 0058), wherein the code data stored in the plurality of code blocks is identical data (store multiple copies of memory management data, such as boot code; 0058), and wherein the memory die comprises a plurality of memory planes (multiple planes on die; 0005-0009, 0046-0047), and the plurality of code blocks are stored in different memory planes (data are stored in different planes for parallel/simultaneous operation, 0005, 0006, 0008, 0009, 0044); and a memory controller coupled to the memory device (memory controller coupled to memory array; 0010, 0038, 0040-0044; Fig. 1), wherein, the memory controller is configured to at least: read a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation (reading data blocks on different planes simultaneously; 0005, 0006, 0012, 0044).
Ravimohan does not suggest the controller combine the portion of the code data read from each code block of the at least the portion of code blocks into complete code data according to a preset rule.
Liang teaches a flash memory system wherein the devices have multiple planes, each plane storing multiple pages (0015), wherein the data portion on the different planes can be simultaneously read (0079, 0084; Fig. 6-7). These read data portions are combined to reconstruct a data (0084-0085) using according to the XOR function/rule (0071-0075). Liang is an analogous art that is the field of performing parallel operations to memory having multiple planes, increasing memory access parallelism and faster memory operations (abstract, 0002, 0015). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Liang’s teaching of combining the data read on the different memory planes to form a complete data according to a rule, in the invention of Ravimohan, to increase memory access parallelism and faster memory access operations.
As to claim 4, 14:
Ravimohan teaches the memory controller is configured to: determine the plurality of code blocks from a plurality of blocks of the memory die before reading the portion of code data of each code block of at least a portion of code blocks simultaneously (access memory management data for metablocks containing management data such as mapping data and boot code data on different planes; 0010, 0012, 0052, 0058; use management data to read data blocks on different planes simultaneously; 0005, 0006, 0010, 0012, 0044).
As to claim 7, 17:
Ravimohan teaches the memory controller is configured to: perform related operations after power-on or related operations of exiting a low power consumption mode using the complete code data (perform reading data blocks on different planes simultaneously; 0005, 0006, 0012, 0044, 0051; data blocks may contain access memory system management data, such as boot code, a data used during power on; 0052, 0058).
As to claim 8, 18:
Ravimohan teaches the memory controller is further configured to: after reading the portion of code data of each code block of at least a portion of code blocks simultaneously, check whether the read portion of code data of each code block is correct (perform error correction ECC algorithm to check for error on data read; 0041).
As to claim 9, 19:
Ravimohan teaches the memory controller is further configured to: when there is error in the read portion of code data of each code block, replace the code block to which an erroneous code data belongs, and read the replaced code block (identify error in data read and correct any error; 0041).
As to claim 10:
Ravimohan teaches the memory system comprises a solid state disk (solid state memory/disk; 0002, 0005, 0027-0029).
As to claim 11:
Ravimohan teaches an operation method for a memory system (method; 0009, claims), the operation method comprising: reading a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation, wherein the read portion of code data of each code block constitutes complete code data stored in one code block (reading data blocks on different planes simultaneously; 0005, 0006, 0012, 0044; data blocks being memory management data containing multiple copies of boot data; 0058).
Ravimohan does not suggest the controller combine the portion of the code data read from each code block of the at least the portion of code blocks into complete code data according to a preset rule.
Liang teaches a flash memory system wherein the devices have multiple planes, each plane storing multiple pages (0015), wherein the data portion on the different planes can be simultaneously read (0079, 0084; Fig. 6-7). These read data portions are combined to reconstruct a data (0084-0085) using according to the XOR function/rule (0071-0075). Liang is an analogous art that is the field of performing parallel operations to memory having multiple planes, increasing memory access parallelism and faster memory operations (abstract, 0002, 0015). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to use Liang’s teaching of combining the data read on the different memory planes to form a complete data according to a rule, in the invention of Ravimohan, to increase memory access parallelism and faster memory access operations.
Allowable Subject Matter
Claims 2, 3, 5-6, 12-13, and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 2/12, the prior art does not suggest the memory system according to claim 1/11, wherein a number of the plurality of code blocks is M; each of the code blocks comprises N code pages; wherein M and N are positive integers greater than 1; the memory controller is configured to: if M is equal to N, read code data of one code page of each of the code blocks simultaneously according to a first preset rule; if M is greater than N, read code data of one code page of each of the code blocks of N code blocks simultaneously according to a second preset rule; and if M is less than N, for a first to an i-th times, read the code data of one code page of each of the code blocks simultaneously each time according to a third preset rule; for an i+1-th time, read code data of one code page of each of the code blocks of j code blocks simultaneously; wherein (i+1) is an quotient of N divided by M, and j is a remainder of N divided by M, wherein, the code data read from each of the code pages is different.
As to claim 5/15, the prior art does not further suggest the memory system according to claim 4/11, wherein each of the memory planes includes blocks including the code block, each block of the blocks includes a preset memory page; and wherein the memory controller is configured to: read preset memory pages of all blocks; and determine a block of which a corresponding preset memory page stores a tag indicating information of code block to be the code block.
Claims 3, 6, 13, and 16 are also allowable for incorporating the limitations of the parent claim 2/5/12/15, and further limitations.
Conclusion
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/THAN NGUYEN/Primary Examiner, Art Unit 2138