DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 2, 5 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 2, the claim limitation “…the oscillator array comprises the oscillators arranged in an NxN square matrix;…..in the sub-millimeter wave band…” is being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention because –
(i). the first underlined portion of the claim limitation “the oscillators” should be “the plurality of oscillators” according to antecedent basis requirement;
(ii). the term “N” has not been defined; and
(iii). there is insufficient antecedent basis for the third underlined portion of the claim limitation “the sub-millimeter wave band”.
Regarding claim 5, the claim limitation “…the corners of the NxN array…” is being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention because –
(i). there is insufficient antecedent basis for the claim limitation “the corners”;
(ii). the term “N” has not been defined; and
(iii). there is insufficient antecedent basis for the claim limitation “the NxN array”.
Regarding claim 6, the claim limitation “…the same row or the same column of the NxN array…” is being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention because –
(i). there is insufficient antecedent basis for the claim limitation “the same row” and “the same column”;
(ii). the term “N” has not been defined; and
(iii). there is insufficient antecedent basis for the claim limitation “the NxN array”.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hisaaki et a. (JP 2008-289098) (hereinafter “Hisaaki”).
Regarding claim 1, Hisaaki discloses an injection locked oscillator array circuit device (Fig.7, please refer to the whole reference for detailed), comprising: an oscillator array (formed by 1s, 1A, 1B, 1C and 1D in Fig.7) comprising a plurality of oscillators arranged in a square matrix (5 x 5 square matrix formed by 1s, 1A, 1B, 1C and 1D shown in Fig.7); an injection locking circuit (formed by 3A, 3B, 3C, 3D, 4A, 4B, 4C and 4D) configured to inject an injection locking signal (signal output from 4A, 4B, 4C and/or 4D; Note: according to Application’s specification page 4, line 25 - which states “A singular form used in this specification includes a plural form”) into some of the oscillators (1A, 1B, 1C and/or 1D, respectively) in the oscillator array (formed by 1s, 1A, 1B, 1C and 1D in Fig.7).
Regarding claim 3, Hisaaki discloses the injection locking circuit is configured to inject the injection locking signal (signal output from 4A, 4B, 4C and 4D) into some of the oscillators (1A, 1B, 1C and 1D) located a symmetric structure (at four corners shown in Fig.7) within the oscillator array (formed by 1s, 1A, 1B, 1C and 1D in Fig.7).
Regarding claim 7, Hisaaki discloses a method of designed an injection-locked oscillator circuit (Fig.7, please refer to the whole reference for detailed), comprising the step of: arranging a plurality of oscillators (1s, 1A, 1B, 1C and 1D in Fig.7) to form a square matrix (5 x 5 square matrix formed by 1s, 1A, 1B, 1C and 1D shown in Fig.7); placing an injection locking circuit (formed by 3A, 3B, 3C, 3D, 4A, 4B, 4C and 4D) to inject an injection locking signal (signal output from 4A, 4B, 4C and/or 4D; Note: according to Application’s specification page 4, line 25 - which states “A singular form used in this specification includes a plural form”) into some of the oscillators (1A, 1B, 1C and/or 1D, respectively) in the square matrix; wherein the oscillators into which the injection locking signal is injected are located in a symmetric structure (at four corners shown in Fig.7).
6. Claims 1, 3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain et al. (2020/0119742) (“Jain”).
Regarding claim 1, Jain discloses an injection locked oscillator array circuit device (Fig.1A, please refer to the whole reference for detailed), comprising: an oscillator array (formed by ILOs of 1-4 in Fig.1A) comprising a plurality of oscillators (ILOs) arranged in a square matrix (2 x 2 square matrix formed by ILOS shown in Fig.1A); an injection locking circuit (formed by fref, Master PLL, Muli-phase clock pulse generator and injection-locked detector) configured to inject an injection locking signal (signal output from multi-phase clock pulse generator; Note: according to Application’s specification page 4, line 25 - which states “A singular form used in this specification includes a plural form”) into some of the oscillators (some of ILOs) in the oscillator array (ILOs).
Regarding claim 3, Jain discloses the injection locking circuit (formed by fref, Master PLL, Muli-phase clock pulse generator and injection-locked detector) is configured to inject the injection locking signal (signal output from multi-phase clock pulse generator) into some of the oscillators (some of ILOs) located a symmetric structure (Fig.1A) within the oscillator array (formed by ILOs of 1-4 in Fig.1A).
Regarding claim 7, Jain discloses a method of designed an injection-locked oscillator circuit (Fig.1A, please refer to the whole reference for detailed), comprising the step of: arranging a plurality of oscillators (ILOs of 1-4 in Fig.1A) to form a square matrix (2 x 2 square matrix formed by ILOS shown in Fig.1A); placing an injection locking circuit (formed by fref, Master PLL, Muli-phase clock pulse generator and injection-locked detector) to inject an injection locking signal (signal output from multi-phase clock pulse generator; Note: according to Application’s specification page 4, line 25 - which states “A singular form used in this specification includes a plural form”) into some of the oscillators (some of ILOs) in the square matrix; wherein the oscillators into which the injection locking signal is injected are located in a symmetric structure (Fig.1A).
7. Claims 1, 3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenji et a. (JP 2006-94333) (hereinafter “Kenji”).
Regarding claim 1, Kenji discloses an injection locked oscillator array circuit device (Fig.9, please refer the whole reference for detailed), comprising: an oscillator array (for example formed by 3a, 3b, 6a and 6b) comprising a plurality of oscillators (3a, 3b, 6a and 6b) arranged in a square matrix (2x2 matrix formed by 3a, 3b, 6a and 6b); an injection locking circuit (1, 2 and the circuits (wire lines) connected to 3a, 3b, 6a and 6b) configured to inject an injection locking signal into some of the oscillators (3a, 3b, 6a and/or 6b) in the oscillator array (3a, 3b, 6a and 6b).
Regarding claim 3, Kenji discloses the injection locking circuit (1, 2 and the circuits (wire lines) connected to 3a, 3b, 6a and 6b) is configured to inject the injection locking signal into some of the oscillators located a symmetric structure within the oscillator array (3a, 3b, 6a and 6b).
Regarding claim 7, Kenji discloses a method of designed an injection-locked oscillator circuit (Fig.9, please refer the whole reference for detailed), comprising the step of: arranging a plurality of oscillators (for example formed by 3a, 3b, 6a and 6b) to form a square matrix (2x2 matrix formed by 3a, 3b, 6a and 6b); placing an injection locking circuit (1, 2 and the circuits (wire lines) connected to 3a, 3b, 6a and 6b) to inject an injection locking signal into some of the oscillators (3a, 3b, 6a and/or 6b) in the square matrix; wherein the oscillators into which the injection locking signal is injected are located in a symmetric structure (3a, 3b, 6a and 6b in Fig.9).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hisaaki et a. (JP 2008-289098) (hereinafter “Hisaaki”) in view of Jain et al. (2020/0119742) (“Jain”).
Regarding claim 2, Hisaaki is used to reject claim 1 above.
Hisaaki discloses the oscillator array (formed by 1s, 1A, 1B, 1C and 1D in Fig.7) comprises the oscillators arranged in an N×N square matrix (5 x 5 square matrix formed by 1s, 1A, 1B, 1C and 1D shown in Fig.7), each oscillator forming the oscillator array is phase-coupled to each other via a coupling network (coupling network between each of the oscillators in the oscillator array; please refer to at least ¶ 82-88), the oscillators are injected-locked oscillators operating in the millimeter wave band (please refer to at least ¶ 2, 3 and 90).
Hisaaki doesn’t explicitly disclose the oscillators are injected-locked oscillators operating in the sub-millimeter wave band of 300 GHz or higher.
Jain discloses an example of a millimeter wave frequency bands is in the range of 30 GHz to 300 GHz (please refer to at least ¶ 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hisaaki with the teaching of Jain to provide the oscillators are injected-locked oscillators operating in the sub-millimeter wave band of 300 GHz or higher. The suggestion/motivation would have been to provide a certain millimeter wave frequency as a design choice.
11. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kenji et a. (JP 2006-94333) (hereinafter “Kenji”) in view of Fujita (8,314,742).
Regarding claim 4, Kenji is used to reject claims 1 and 3 above.
Kenji discloses the injection locking circuit comprises: a first power divider (2) configured to distribute the injection locking signal.
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Kenji doesn’t explicitly disclose a first power divider configured to output the distributed signals through a first transmission line and a second transmission line; a second power divider configured to distribute the signal delivered through the first transmission line and inject the distributed signals into a first oscillator and a second oscillator among the oscillators via a third transmission line and a fourth transmission line; and a third power divider configured to distribute the signal delivered through the second transmission line and inject the distributed signals into a third oscillator and a fourth oscillator among the oscillators via a fifth transmission line and a sixth transmission line.
Fujita discloses an example of a power divider (13 in Fig.1 and 2) configured to distribute a signal (signal from 11) and output the distributed signals through a first transmission line (131 in Fig.2) and a second transmission line (132).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kenji with the teaching of Fujita to provide a first power divider, a second power divider and a third power divider (where Fujita discloses an example of power divider) at the locations stated by the Examiner’s notes over Kenji’s Fig.9 above. The suggestion/motivation would have been to use power divider to divide the signal.
Regarding claim 5, Kenji in view of Fujita is used to reject claims 1, 3 and 4 above.
Kenji discloses the first oscillator (3a in Fig.9), the second oscillator (3b), the third oscillator (6a) and the fourth oscillator (6b) are oscillators located at the corners of the N×N array (if 2x2 array).
Allowable Subject Matter
12. Claim 6 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD TAN whose telephone number is (571)270-7455. The examiner can normally be reached on M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Richard Tan/Primary Examiner 2849