DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 7/13/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bowers 4675561.
With respect to claim 1, figure 6 of Bowers discloses a voltage follower [Fig. 6] having a first input terminal [V IN/62] and a first output terminal [V OUT/64],
the voltage follower comprising:
a transistor [FET 1] having a gate, a source, a drain, and a body, wherein the gate is coupled to the first input terminal [62], the source is coupled to the first output terminal [64], and the drain is coupled to a first reference voltage [V+];
a first load [I1] coupled between the source and a second reference voltage [V-/GND]; and
a buffer circuit [FET2, I2] having a second input terminal [gate FET 2] and a second output terminal [source FET 2], wherein the second input terminal is coupled to the gate, and the second output terminal is coupled to the body [coupled by 72];
wherein a voltage difference between the source and the gate is substantially equal to a voltage
difference between the second output terminal and the second input terminal. [Col. 4, lines 41-54: I1 can be scaled considerably differently from I2 if the FETs are similarly scaled so as to produce comparable current densities and source voltages for the two FETs at low output load levels. For example, if the I1 current is ten times the I2 current, FET 1 would be scaled about ten times larger than FET 2, resulting in balanced voltages at the two FET sources.]
With respect to claim 2, figure 6 of Bowers discloses the voltage follower of claim 1, wherein the source is not electrically connected to the body.
With respect to claim 10, figure 6 of Bowers discloses the voltage follower of claim 1, wherein the first load is a resistor, a current source, or a diode-connected metal-oxide-semiconductor field-effect transistor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bowers 4675561 in view of Kurahashi et al. 20220029632.
With respect to claim 11, figure 6 of Bowers discloses a voltage follower having a first input terminal [V IN / 62],
a first output terminal [V OUT / 64], the voltage follower comprising:
a first transistor [FET 1] having a first gate, a first source, a first drain, and a first body, wherein the first gate is coupled to the first input terminal [V IN], the first source is coupled to the first output terminal,
and the first drain is coupled to a first reference voltage [V+];
a first load [I1] coupled between the first source and a second reference voltage [V- / 66 / GND];
a first buffer circuit [FET 2, I2] having a third input terminal [gate FET 2] and a third output terminal [source FET2], wherein the third input terminal is coupled to the first gate [V IN / 62], and the third output terminal [coupled by 72] is coupled to the first body;
Bowers does not disclose:
a second input terminal, and a second output terminal,
a second transistor having a second gate, a second source, a second drain, and a second body,
wherein the second gate is coupled to the second input terminal, the second source is coupled
to the second output terminal, and the second drain is coupled to the first reference voltage;
a second load coupled between the second source and the second reference voltage; and
a second buffer circuit having a fourth input terminal and a fourth output terminal, wherein the
fourth input terminal is coupled to the second gate, and the fourth output terminal is coupled
to the second body:
wherein a voltage difference between the first source and the first gate is substantially equal to
a voltage difference between the third output terminal and the third input terminal, and a
voltage difference between the second source and the second gate is substantially equal to a
voltage difference between the fourth output terminal and the fourth input terminal.
However, figure 2A of Kurahashi et al. discloses differential voltage follower circuits.
It would have been obvious to one skilled in the art at the time the invention was made to
repeat the above structure to accommodate a differential input signal since it was a known
technique in the art.
With respect to claim 12, the above modification discloses the voltage follower of claim 11, wherein the first source is not electrically connected to the first body, and the second source is not electrically connected to the second
body.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bowers [4675561] in view of Kurahashi et al. [20220029632] and further in view of Mitsuda et al. [20130300494]
With respect to claim 14, the above modification discloses the voltage follower of claim 12, but does not disclose the voltage follower further comprising:
a third load coupled between the first drain and the first reference voltage; and
a fourth load coupled between the second drain and the first reference voltage.
However, Figure 1 of Mitsuda et al. discloses a second load [TP4] coupled between the first drain and the first reference voltage.
It would have been obvious to one skilled in the art before the effective filing date of the application to add an additional load TP4 as seen in Mitsuda et al. to the differential voltage followers in claim 12, to control current on the drain side of the voltage follower since it was a known technique in the art.
With respect to claim 4, the above modification discloses the voltage follower of claim 2, further comprising: a second load coupled between the drain and the first reference voltage.
Allowable Subject Matter
Claim 21 is allowed.
Claims 5-9, 15-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached on 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2836
10/1/26
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