Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on January 22,2025.
2. Claims 1-25 are pending and has been examined.
Information Disclosure Statement
3.The information disclosure statement (IDS) submitted on 04/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. The drawings submitted on 01/22/2025 are acceptable.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-16 and 19-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites “the open loop transfer” in the claim. There is insufficient antecedent basis for this claim limitation.
Claim 16 recites “Wo” in the claim and dependent on claim 14. However, claim 14 doesn’t introduce unity gain frequency “Wo” in the claim. Examiner noted that the dependency of claim 16 should be on either on claim 13 or 15 because unity gain frequency “Wo” introduce in their claims . For the purpose of this examination, examiner decide not to examine claim 16 until applicant resolve this issue. Appropriated action is required.
Claim 19 recites “the first PWM signal” and “the second PWM signal” in lines 6 and 12, respectively . There are insufficient antecedent basis for these claim limitation.
Claim 25 recites “the first PWM signal generator ” and “the second PWM signal generator ” in lines 10-12, respectively . There are insufficient antecedent basis for these claim limitation.
Claims 20-24 dependent on claim 19, thus are also rejected because of their dependency.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11,17 and 25 are rejected under 35 U.S.C. 102(a)(1) (a)(1) as being anticipated by Ihs “20160359411”.
In regarding to claim 1, His discloses a digitally controlled DC-DC converter (Figs. 1-7: a digitally controlled DC-DC converter , see parg.00004), comprising: a high side switch and a low side switch coupled in series (high side switch 113a and low side switch 113b connected in series see parag.0019), with a first end of an output inductor coupled to a node between the high side switch and the low side switch ((a first end of output inductor I 15 is connected to the node between high side switch 113a and law side
switch 113b; paragraph [00201) and a second end of the output inductor providing a regulated output for a load, with an output capacitor coupled to the second end of the output inductor ( output of inductor 115 is coupled to output capacitor 117, which supplies a regulated load output; paragraph [0020]);;
a first pulse width modulation (PWM) signal generator configured to generate a first PWM signal having a first duty cycle;
a second PWM signal generator configured to generate a second PWM signal having a second duty cycle (second pulse width (PWM) modulation generator 125b produces pulses with a second duty cycle; paragraph [0022]),,
the second duty cycle greater than the first duty cycle ((signals from
the second PWM generator 125b have an increased duty cycle relative to pulse from PWM generator 125n; paragraph [0024]);)
logic circuitry to select either the first PWM signal or the second PWM signal for use in controlling the high side switch and the low side switch (the logic block 121 may receive the signal produced by the comparator 123, and the pulses. produced by the first and second PWM generators 125a and 125b to control state of the high side and low side switches 113a and 113 b; paragraph (0024]};; and
gain circuitry coupled as feedback from the second end of the output inductor to the first PWM signal generator and the second PWM signal generator (gain block 415 provides feedback from the output inductor the PMW generators 125a and 125b; para. [0041]),.
In regarding to claim 2, Ihs discloses (Figs. 1-7) further comprising a first comparator coupled to the regulated output, the first comparator configured to compare voltage of the regulated output with a first predefined voltage (comparator 123
Receives an input from the output of inductor 115 and a reference voltage [first predetermined voltage]:parag. [0021]), an output of the first comparator coupled to the logic circuitry for use in selecting the first PWM signal or the second PWM signal for use in controlling the high side switch and the low side switch (logic block 121 receives outputs from comparator 123 to select the proper PWM 125a or 125b for
Controlling the high and low side switches 113a and 113b; paragraph [0024]).
In regarding to claim 3, Ihs discloses (Figs. 1-7), wherein the first predefined voltage is a desired output voltage of the DC-DC converter minus a first tolerance voltage (the reference voltage [first predetermined voltage] has a magnitude equal
To the desired output voltage of the DC-DC converter , minus a tolerance amount; paragraph [0021])..
In regarding to claim 4, Ihs discloses (Figs. 1-7), wherein the first PWM generator and the second PWM generator are each first order unconditionally stable (the PMW generator 125a and b provide a first order unconditionally stable loop;
paragraph [0038])..
In regarding to claim 5, Ihs discloses (Figs. 1-7), wherein each of the first PWM generator and the second PWM generator include circuitry for causing the first duty cycle and the second duty cycle, respectively (PMW generators 125a and b contain circuitry to cause the first and second duty cycles; Fig. 1, paragraph [0022]),, to track variations in voltage supplied to the high side switch (the loop provides an output PWM duty cycle which track variation in input voltage to the high side switch 113a; paragraph [0038]).
In regarding to claim 6, Ihs discloses (Figs. 1-7), wherein the first PWM generator is configured to generate the first PWM signal based on a first reference signal input having a voltage equal to a desired output voltage of the DC-DC converter plus a bias voltage ((the first PWM generator 125a receives a reference voltage Vref_A, where Vref._A is the desired output voltage of the DC-DC converter plus a bias offset; pagraph [0022]).
In regarding to claim 7, Ihs discloses (Figs. 1-7), wherein the bias voltage is approximately ten percent of the desired output voltage (the desired output voltage of the DC-DC converter plus a bias offset, which may be for example about ten
percent of the desired output voltage of the DC-DC converter 123; paragraph [0022]).
n regarding to claim 8, Ihs discloses (Figs. 1-7), wherein the second PWM generator is configured to generate the second PWM signal based on second reference signal input having a voltage equal to the desired output voltage of the DC-DC converter plus the bias voltage plus an adjustment voltage (the second PWM generator 125b receives a reference voltage Vref_B, where Vref_B is the desired output voltage of the DC-DC converter plus a bias offset, plus un adjustment amount; paragraph [0022]).
In regarding to claim 9, Ihs discloses (Figs. 1-7), further comprising a bypass switch coupling the first end and the second end of the output inductor (bypass switch 220 is coupled to the first and second ends of output inductor 215 [which is similar
to output inductor 115]; Fig. 2, parag [0026]-[0028])..
In regarding to claim 10, Ihs discloses (Figs. 1-7), further comprising a second comparator coupled to the regulated output (second comparator 224 coupled to the regulated output of the inductor 215; Fig. 2, paragraph [0026]),, the second comparator configured to compare voltage of the regulated output with a second predefined voltage (comparator 224 determines whether the output voltage is greater than or less than the second reference voltage; paragraph [0029]), and wherein a state of the bypass switch is based on an output of the second comparator (comparator 224 controls the state of the bypass switch based on !he voltage comparison; paragraph [0032])..
In regarding to claim 11, Ihs discloses (Figs. 1-7), wherein the second predefined voltage is a desired output voltage of the DC-DC converter plus a second tolerance voltage (the second reference voltage may be a desired output voltage of
the DC-DC converter plus a voltage tolerance; paragraph (0039]}..
In regarding to claim 17, Ihs discloses (Figs. 1-7), where the gain circuitry comprises two capacitors across an integrator op amp (integrator 311 comprises an operational amplifier coupled between capacitors 321 and its inverting input; parag
[0039]).
In regarding to claim 25, His discloses a digitally controlled DC-DC converter (Figs. 1-7 : a digitally controlled DC-DC converter [00041]), comprising: a high side switch and a low side switch coupled in series (high-side switch 113a and low side switch 113b connected in series; paragraph [0019]), with a first end of an output inductor coupled to a node between the high side switch and the low side switch (a first end
of output inductor 115 is connected to the node between high side switch 113a and low side switch 113b;parag. [0020]) and a second end of the output inductor providing a regulated output for a load, with an output capacitor coupled to the second end of the output inductor (output of inductor 115 is coupled
to output capacitor 117, which supplies a regula1ed load output; paragraph [0020]);;
a plurality of pulse width modulation (PWM) signal generators each configured to generate a PWM signal having a duty cycle of a different duration (first and second pulse width {PWM} modulation generator 125a and 125b produce pulses with a first duty cycle and a second duty cycle; paragraph [0022]);;
circuitry to select a one of the PWM signals for use in controlling the high side switch and the low side switch based on a measure of the regulated output (the logic block 121 may receive the signal produced by the comparator 123, and the
pulses produced by the first and second PWM generator 125a and 125b to control the state of the high side and low side switches 113a and 113b; paragraph [0024]); and
gain circuitry coupled as feedback from the second end of the output inductor to the first PWM signal generator and the second PWM signal generator (gain
block 415 provides feedback from the output inductor of the PMW generators 125a and 125b, paraga [0041]).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12,14 and 19-24 are rejected under 35 U.S.C. 103 as being unpatentable over Ihs “20160359411” in a view of Shah “20120306575”.
In regarding to claim 12 His discloses (Figs. 1-7) , where the gain circuitry is a DC but fail to discloses blocking high pass filter.
Whereas, Shah discloses where the gain circuitry is a DC but fail to discloses blocking high pass filter (the gain element include a high-pass filter for DC blocking;
paraphs {0052], [0055]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the DC-DC converter of Ihs to include blocking high pass filter as taught by Shah because an advantage to obtain a noise reduction and improved signal clarity.
In regarding to claim 14 His discloses (Figs. 1-7) but fails to discloses where the high pass filter has attention of up to -40 dB.
Whereas, Shah discloses the high pass filter has is attention (the frequency of the high pass filter can range from 2 Hz to 40 kHz; paragraph [0040]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the DC-DC converter of Ihs to include attention of up to -40 dB, since where the general conditions of the claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art.
In regarding to claim 19, His discloses (Figs. 1-7), a method of controlling a switching DC-DC converter ((a digitally Controller DC-DC converter: paragraph [0004])., comprising:
generating a first pulse width modulation (PWM) signal having a first duty cycle (first pulse width (PWM} modulation generator 125a produces pulses with a first duty cycle; paragraph [0022]);
generating a second PWM signal having a second duty cycle, the second duty cycle having a different duration than the first duty cycle (second pulse width (PWM) modulation generator i25b produces pulses: with a second duty cycle; paragraph [0022]);
controlling operation of at least some switches of the switching DC-DC converter based on the first PWM signal if an output voltage of the DC-DC converter is below a first predefined voltage level (the logic block 121 may receive the signal produced by the comparator 123, and the pulses produced by first
PWM generator 125a to control state of the high side and low side switches 113a and b based on the first reference voltage; paragraph [0024]);;
controlling operation of the at least some switches of the switching DC-DC converter based on the second PWM signal if the output voltage of the DC-DC converter is above the first predefined voltage level (the logic block 121 may receive the signal produced by the compar,123 and the pulses produced by second PWM generator 125b to control state of the high side and low side switches 113a and b based on the second reference voltage; paragraph [0024]);; and
feeding back a high pass filter gain function from the output voltage to the first PWM signal and the second PWM signal (gain block 415 provides feedback from the output inductor the PMW generators 125a and b: paragraph [0041]) but fail to disclose a high pass filter.
Whereas, Shah discloses a high pass filler (the gain element include a high-pass filter for DC blocking; parag [0052], [0055]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the DC-DC converter of Ihs to include blocking high pass filter as taught by Shah because the advantage to obtain a noise reduction and improved signal clarity.
In regarding to claim 20, His discloses (Figs.1-7) wherein the at least some switches of the switching DC-DC converter are a high side switch and a low side switch (high-side switch 113a and low side switch 113b connected in series; paragraph [0019 ])., with a node between the high side switch and the low side switch providing a node for coupling to an output inductor of the switching DC- DC converter (a first end of output inductor I 15 is connected to the node between high side switch 113a and low side switch 113b; paragraph [0020]).
In regarding to claim 21, Ihs discloses (Figs.1-7) further comprising coupling ends of the output inductor of the switching DC-DC converter if the output voltage of the DC-DC converter is above a second predefined voltage level (the logic block: 121 may receive !he signal produced by the comparator 123, and the pulses produce by
Second PWM gererator 125b to control state: of the high side and low side switches 113a and 113b based on the second reference voltage; parag. [0024]),.
In regarding to claim 22, Ihs discloses (Figs.1-7) further comprising opening the high side switch and the low side switch if the output voltage of the DC-DC converter is above the second predefined voltage level (the logic block 121 may receive
the signal produced by the comparator 123, and the pulses produced by second PWM generator 125b to control state of thigh side and low side switch 113a and 113b based on the second reference voltage, parag. [0024])
In regarding to claim 23, Ihs discloses (Figs.1-7) wherein the first predefined voltage level is a desired DC-DC converter output voltage minus a first voltage tolerance (the reference voltage [first predetermined voltage] has a magnitude equal to the desired output voltage of the DC-DC converter , minus a tolerance amount paragraph [0021])..
In regarding to claim 24, Ihs discloses (Figs.1-7)wherein the second predefined voltage level a desired DC-DC converter output voltage plus a second voltage tolerance (the second PWM generator 125b receives a reference voltage Vref_B, where
Vref_B is the desired output voltage of the DC-DC converter plus a bias offset, plus an adjustment amount; paragraph [0022))..
8. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ihs “20160359411” in a view of Ihs “20160049860”. Hereafter Ihs “9860”
In regarding to claim 18, Ihs discloses (Figs.1-7), where the gain circuitry provides inputs to sawtooth generators in the first and second PWM signal generator (gain block 415 provides feedback from the output inductor the PMW generators 125a and 125b; para. [0041]) but fails to disclose sawtooth generator,
Whereas, Ihs “9860” discloses sawtooth generators (sawtooth signal generators; paragraph [0048])
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the DC-DC converter of Ihs to include sawtooth generator as taught by Ihs “9860” in order to produce synchronized waveform.
Allowable Subject Matter
9. Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 13 is objected because the prior art of record fails to disclose or suggest the digital controlled DC-DC converter including the limitation of “where the high pass filter has a transfer function of
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Claim 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
In regarding to claim 15, the prior art of record fails to disclose or suggest the digital controlled DC-DC converter including the limitation of “ where the open loop transfer function is
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Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
Prosecution Insights