Prosecution Insights
Last updated: October 21, 2026
Application No. 19/034,530

CONTROLLER APPLIED TO AN LLC RESONANT POWER CONVERTER

Non-Final OA §102§103
Filed
Jan 22, 2025
Priority
Dec 16, 2024 — TW 113148845
Examiner
CAULK, JENNIFER CHRISTINE
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Leadtrend Technology Corp.
OA Round
1 (Non-Final)
97%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 97% — above average
97%
Career Allowance Rate
38 granted / 39 resolved
+29.4% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
22 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
48.2%
+8.2% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 39 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings The drawings are objected to because: Fig 1: this drawing is missing label “101” for the dashed box around the optocoupler, per the specification [0030]. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following limitations must be shown or the feature(s) canceled from the claim(s): Claim 1: “a threshold voltage generation circuit for generating an upper threshold voltage and a lower threshold voltage according to … a gate control signal phase”. Fig 3 does not show the gate control signal phase GP at all. The thresholds are generated without any dependency on GP. Claim 3: “a compensation circuit for receiving a compensation voltage and the reference voltage, wherein the compensation circuit outputs a first voltage according to the first phase, the compensation voltage and the reference voltage, and outputs a second voltage according to the second phase, the compensation voltage and the reference voltage”. Fig 3 does not show the gate control signal phase GP at all. The thresholds are generated without any dependency on GP. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The disclosure is objected to because of the following informalities: [0029]: “When a gate control signal phase GP inputted into the compensation circuit 2022 is a first phase, the compensation circuit 2022 outputs the first voltage VCM-AVFBC PD, and when the gate control signal phase GP is a second phase, the compensation circuit 2022 outputs the second voltage VCM+AVFBC PD, wherein the first phase corresponds to the upper bridge control signal HGATE, and the second phase corresponds to the lower bridge control signal LGATE.” This passage describes the signal GP as an input to 2022, but Fig 3 has no such input or a way to select a voltage based on phase. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 6-9 and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kikuchi (US 20200169160 A1). Regarding Claim 1, Kikuchi discloses a controller applied to an LLC resonant power converter (power control IC 2 controls LLC resonant converter 52, Fig 1), comprising: a threshold voltage generation circuit (21 and 22, Fig 2) for generating an upper threshold voltage and a lower threshold voltage according to a reference voltage (21 and 22 generate VTHH' and VTHL' according to predetermined reference voltage V212/Vnc, Fig 3), a feedback voltage (Vfb, Fig 2/3) and a gate control signal phase (control signals to SW221/SW222 inside of 22 to convert VTHH/VTHL into VTHH'/VTHL;, Fig 2/6, [0104-0111]); and a gate control signal generation circuit (24, 25, and 27, Fig 2/10) for disabling an upper bridge control signal (GH, Fig 2) according to a sensing voltage (VCR', Fig 2) and the upper threshold voltage (24 compares VTHH' with VCR' and sends H_OFF to 27, Fig 2, [0118-0121])) or disabling a lower bridge control signal according to the sensing voltage and the lower threshold voltage (25 compares VTHL' with VCR' and sends L_OFF to 27, Fig 2, [0118-0121]), wherein an upper bridge switch of the LLC resonant power converter is turned on according to the upper bridge control signal (Q1 is turned on according to GH, Fig 1, [0133]), and a lower bridge switch of the LLC resonant power converter is turned on according to the lower bridge control signal (Q2 is turned on according to GL, Fig 1, [0136]). Regarding Claim 2, Kikuchi discloses all of the limitations of claim 1, and further discloses a wherein the gate control signal phase is a first phase or a second phase, the first phase corresponds to the upper bridge control signal ("at the time point t81 at which the gate driving signal GH is switched from Low to High and the switching element Q1 is turned from off to on", Fig 8, [0105]) and the second phase corresponds to the lower bridge control signal ("at a time point t91 at which the gate driving signal GL is switched from Low to High and the switching element Q2 is turned from off to on", Fig 9, [0109]). Regarding Claim 6, Kikuchi discloses all of the limitations of claim 1, and further discloses a wherein the gate control signal generation circuit comprises: a first comparator for receiving the sensing voltage and the upper threshold voltage and generating a first disabling signal according to the sensing voltage and the upper threshold voltage (24 receives VCR' and VTHH' to generate H_OFF, Fig 2, [0118]); a second comparator for receiving the sensing voltage and the lower threshold voltage and generating a second disabling signal according to the sensing voltage and the lower threshold voltage (25 receives VCR' and VTHL' to generate L_OFF, Fig 2, [0118]); a first flip-flop coupled to the first comparator, wherein the first flip-flop controls disabling and enabling of the upper bridge control signal according to the first disabling signal and an upper bridge enabling signal, respectively (flip flop DH receives H_OFF from 24 and QH to control Q1 with GH, Fig 2, [0120, 1033]); and a second flip-flop coupled to the second comparator, wherein the second flip-flop controls disabling and enabling of the lower bridge control signal according to the second disabling signal and a lower bridge enabling signal, respectively (flip flop DH receives H_OFF from 24 and QH to control Q1 with GH, Fig 2, [0121, 1036]). Regarding Claim 7, Kikuchi discloses all of the limitations of claim 1, and further discloses a wherein the upper threshold voltage is greater than the reference voltage and the lower threshold voltage is less than the reference voltage (V212/Vnc is 2V and VTHH' is greater than V212/Vnc and VTHL' is less than Vnc, Fig 16, [0161-2]). Regarding Claim 8, Kikuchi discloses all of the limitations of claim 1, and further discloses a wherein the power converter is a current mode LLC resonant power converter (the LLC resonant converter 52 includes a feedback path that uses the resonant current detection signal VIS to enhance the load response, [0080, 0083]). Regarding Claim 9, Kikuchi discloses a controller applied to an LLC resonant power converter (power control IC 2 controls LLC resonant converter 52, Fig 1), comprising: a threshold voltage generation circuit (21 and 22, Fig 2) for generating an upper threshold voltage and a lower threshold voltage according to a reference voltage (21 and 22 generate VTHH' and VTHL' according to predetermined reference voltage V212/Vnc, Fig 3), a feedback voltage (Vfb, Fig 2/3), an upper bridge control signal (GH gates the switch SW221 inside of 22 to convert VTHH into VTHH', Fig 2/6) and a lower bridge control signal (GL gates the switch SW222 inside of 22 to convert VTHL into VTHL, Fig 2/6); and a gate control signal generation circuit (24, 25, and 27, Fig 2/10) for disabling the upper bridge control signal (GH, Fig 2) according to a sensing voltage (VCR', Fig 2) and the upper threshold voltage (24 compares VTHH' with VCR' and sends H_OFF to 27 to reset DH and cause GH to turn off Q1, Fig 2, [0118-0120])) or disabling the lower bridge control signal (GL, Fig 2) according to the sensing voltage and the lower threshold voltage (25 compares VTHL' with VCR' and sends L_OFF to 27 to reset DL and cause GL to turn off Q2, Fig 2, [0118-0121]), wherein an upper bridge switch of the LLC resonant power converter is turned on according to the upper bridge control signal (Q1 is turned on according to GH, Fig 1, [0133]), and a lower bridge switch of the LLC resonant power converter is turned on according to the lower bridge control signal (Q2 is turned on according to GL, Fig 1, [0136]). Regarding claim 13, it is rejected for the same reasons as stated above for Claim 6. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi (US 20200169160 A1) in view of Harshey (US 10784783 B1). Regarding Claim 3, Kikuchi discloses all of the limitations of claim 2, and further discloses a voltage adjustment circuit coupled to the compensation circuit, wherein the voltage adjustment circuit generates the upper threshold voltage according to the feedback voltage and the first voltage, and generates the lower threshold voltage according to the feedback voltage and the second voltage (21 and 22 receive Vfb and resonant current detection values to generate VTHH' and VTHL', Fig 2). Kikuchi does not disclose a compensation circuit for receiving a compensation voltage and the reference voltage, wherein the compensation circuit outputs a first voltage according to the first phase, the compensation voltage and the reference voltage, and outputs a second voltage according to the second phase, the compensation voltage and the reference voltage. Harshey teaches a conventional compensation circuit (see Fig 6-7) including a compensation circuit for receiving a compensation voltage and the reference voltage (node 604 receives Ipk_comp and Ipk_sns, and node 702 receives Ivalley_sns and Ivalley_comp, which are current values that a person having ordinary skill in the art could easily convert to voltage using Kirchoff's law, Fig 6-7), wherein the compensation circuit outputs a first voltage according to the first phase, the compensation voltage and the reference voltage, and outputs a second voltage according to the second phase, the compensation voltage and the reference voltage (Ipk_sns_ref is Ipk_sns - Ipk_comp and generated during the charging phase, and Ivalley_sns_ref is Ivalley_sns + Ivalley_comp and generated during the discharging phase, Fig 6-7, Col 10[55-58] and Col 11[58-61]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the compensation circuit in Kikuchi, as taught by Harshey, as it provides the advantage of adjusting the threshold that disables the upper and lower bridge control signals to account for circuit delays and improve efficiency (Col 9[41]-Col 10[33] of Harshey). Regarding Claim 4, the combination of Kikuchi and Harshey all of the limitations of claim 3, and further discloses wherein the compensation circuit comprises: a first adder for receiving the compensation voltage and the reference voltage and subtracting the compensation voltage from the reference voltage to generate the first voltage (node 604 receives Ipk_comp and Ipk_sns to generate Ipk_sns_ref = Ipk_sns - Ipk_comp, which are current values that a person having ordinary skill in the art could easily convert to voltage using Kirchoff's law, Fig 6-7 of Harshey); and a second adder for receiving the compensation voltage and the reference voltage and adding the compensation voltage to the reference voltage to generate the second voltage (node 702 receives Ivalley_comp and Ivalley_sns to generate Ivalley_sns_ref = Ivalley_sns + Ivalley_comp, which are current values that a person having ordinary skill in the art could easily convert to voltage using Kirchoff's law, Fig 6-7 of Harshey). Regarding Claim 5, the combination of Kikuchi and Harshey discloses wherein the voltage adjustment circuit comprises: a level circuit for generating a voltage level according to the feedback voltage (21 generates VTHH and VTHL according to Vfb, Fig 2 of Kikuchi); and a level shifter coupled to the compensation circuit and the level circuit (22 generates VTHH' by adding VTHH and VIS, Fig 2 of Kikuchi), wherein the level shifter comprises a third adder and a fourth adder, the third adder adds the voltage level to the first voltage to generate the upper threshold voltage (22 generates VTHH' by adding VTHH and VIS/[Ipk_sns_ref of Harshey], Fig 2 of Kikuchi), and the fourth adder subtracts the voltage level from the second voltage to generate the lower threshold voltage (22 generates VTHL' by adding VTHL and VIS/[Ivalley_sns_ref of Harshey], Fig 2 of Kikuchi). Regarding Claim 10, Kikuchi discloses all of the limitations of claim 9, and further discloses wherein the threshold voltage generation circuit comprises: a voltage adjustment circuit coupled to the compensation circuit, wherein the voltage adjustment circuit generates the upper threshold voltage according to the feedback voltage and the first voltage, and generates the lower threshold voltage according to the feedback voltage and the second voltage (21 and 22 receive Vfb and resonant current detection values to generate VTHH' and VTHL', Fig 2). Kikuchi does not disclose a compensation circuit for receiving a compensation voltage, the reference voltage, the upper bridge control signal and the lower bridge control signal, wherein the compensation circuit outputs a first voltage according to the upper bridge control signal, the compensation voltage and the reference voltage, and outputs a second voltage according to the lower bridge control signal, the compensation voltage and the reference voltage. Harshey teaches a conventional compensation circuit (see Fig 6-7) including a compensation circuit for receiving a compensation voltage, the reference voltage, the upper bridge control signal and the lower bridge control signal (node 604 receives Ipk_comp and Ipk_sns and is gated by hs_sns_dr; node 702 receives Ivalley_sns and Ivalley_comp and is gated by hs_dr, ls_sns_dr and ls_dr, which are current values that a person having ordinary skill in the art could easily convert to voltage using Kirchoff's law, Fig 6-7), wherein the compensation circuit outputs a first voltage according to the upper bridge control signal, the compensation voltage and the reference voltage (Ipk_sns_ref is Ipk_sns - Ipk_comp and generated during the charging phase where hs_dr and hs_sns_dr are high, Fig 6/8)., and outputs a second voltage according to the lower bridge control signal, the compensation voltage and the reference voltage (Ivalley_sns_ref is Ivalley_sns + Ivalley_comp and generated during the discharging phase where ls_sns_dr is high, Fig 7/8). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the compensation circuit in Kikuchi, as taught by Harshey, as it provides the advantage of adjusting the threshold that disables the upper and lower bridge control signals to account for circuit delays and improve efficiency (Col 9[41]-Col 10[33] of Harshey). Regarding claim 11, it is rejected for the same reasons as stated above for Claim 5. Regarding claim 12, it is rejected for the same reasons as stated above for Claim 4. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Colbeck (US 20200195155 A1) discloses an LLC half-bridge with GH/GL switch drive signals delayed and shifted relative to an internal switching signal. Yang (US 20250211100 A1) discloses an LLC half-bridge that drives HS/LS switches according to sensed and feedback signals. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.C.C./Examiner, Art Unit 2838 /GARY L LAXTON/Primary Examiner, Art Unit 2838 9/17/2026
Read full office action

Prosecution Timeline

Jan 22, 2025
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
97%
Grant Probability
99%
With Interview (+3.8%)
2y 5m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 39 resolved cases by this examiner. Grant probability derived from career allowance rate.

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