DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 01/23/2025 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 01/23/2025, 04/15/2026 & 06/22/2026. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 & 24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 5 & 24, the limitations cite “further comprising an oscillator configured to generate the clock signal having a frequency corresponding to a number of the plurality of micro control units”, it is unclear how a frequency can be related to the number of circuits e.g., frequency is measured in Hertz while the number circuits is an actual number. For the purpose of prosecutions, it will be treated as “the clock signal frequency is the product of the number of planes and the divided clock frequency”.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 01/23/2025, 04/15/2026 & 06/22/2026. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 12 & 19-24 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Tanizaki et al (US6993696).
Regarding claim 1, Tanizaki discloses a memory apparatus comprising(FIG 2; 20): an instruction memory(50) configured to output a plurality of instruction codes at a predetermined time interval in accordance with a plurality of address signals and a plurality of divided clock signals(FIG 2 & 14; col 6, lines 63-67 discloses ALPG54 comprising an arithmetic unit 90 calculating an address of an instructions that be executed and 142s INT.CLKs e.g., 20/40/80/100 MHZ 20MHz is divided and so on); and a plurality of micro control units coupled to each of a plurality of memory regions(FIG 2-3; 54 comprising 118 and 124 coupled to memory cell array 30) , configured to provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals(118 carry out address scramble on the addresses in X and Y directions according to clocks42s INT.CLKs e.g., 20/40/80/100 MHZ 20MHz is divided and so on) , and configured to perform operations in accordance with corresponding instruction codes among the plurality of instruction codes (FIG 4; col 7, line 5 – col 8 line 13; discloses 118 carry out address scramble of DRAM and address conversion being carried out by logic circuit e.g., 118 based on instructions codes e.g., FIG 4 shows the conversion).
Regarding claim 2, Tanizaki discloses further comprising a divider circuit configured to divide a clock signal to generate the plurality of divided clock signals (FIG 2 & 14; col 9, lines 55-67 discloses 142 generated by multiplying frequency of internal dock signal 140(INT.CLK 20/4/8/100MHz) using PPL in memory).
Regarding claim 3, Tanizaki discloses wherein the divider circuit is configured to generate the plurality of divided clock signals having a predetermined phase difference upon activation of a plane interleave read mode setting signal, and generate the plurality of divided clock signals having a same phase upon deactivation of the plane interleave read mode setting signal (FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phaser with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140).
Regarding claim 4, Tanizaki discloses wherein the divider circuit comprises: a multi-phase signal generator configured to receive the clock signal to output multi-phase signals; a pre-divided clock generator configured to receive the multi-phase signals and the clock signal to output a plurality of pre-divided clock signals; an activation control circuit configured to selectively activate the pre- divided clock generator in response to a reset signal and a plurality of active signals corresponding to each of the plurality of memory regions (FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phaser with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140); and a plurality of multiplexers configured to selectively output the plurality of pre-divided clock signals as the plurality of divided clock signals in accordance with a plane interleave read mode setting signal (FIG 2; multiplexer 44(44 able to control on and off mode e.g., plurality functionalities providing control signals e.g., 64 60).
Regarding claim 5, Tanizaki discloses further comprising an oscillator configured to generate the clock signal having a frequency corresponding to a number of the plurality of micro control units (FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phase with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140, note internal frequency multiplied clock signal 142 is generated by multiplying the frequency of 140 using phase locked loop PLL e.g., oscillator is a key part inside PLL , PLL is feedback control system that uses an internal oscillator to match the frequency with internal clock signal).
Regarding claim 12, Tanizaki discloses a memory apparatus comprising: a plurality of planes(FIG 2 & 4; 30); an input/output pad circuit including a plurality of pads(20); a data input/output circuit coupled with the input/output pad circuit(32); an instruction memory(50) configured to output a plurality of instruction codes at a predetermined time interval in accordance with a plurality of address signals and a plurality of divided clock signals(FIG 2 & 14; col 6, lines 63-67 discloses ALPG54 comprising an arithmetic unit 90 calculating an address of an instructions that be executed and 142s INT.CLKs e.g., 20/40/80/100 MHZ 20MHz is divided and so on); and a plurality of memory operation control related circuits configured to be in common connection with the data input/output circuit(32 34 with 80), be in one-to- one connection with the plurality of planes, provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals(118 carry out address scramble on the addresses in X and Y directions according to clocks42s INT.CLKs e.g., 20/40/80/100 MHZ 20MHz is divided and so on), and perform operations in accordance with corresponding instruction codes among the plurality of instruction codes (FIG 4; col 7, line 5 – col 8 line 13; discloses 118 carry out address scramble of DRAM and address conversion being carried out by logic circuit e.g., 118 based on instructions codes e.g., FIG 4 shows the conversion).
Regarding claim 19, Tanizaki discloses wherein the plurality of memory operation control related circuits are configured to control a program operation and a read operation of the plurality of planes (FIG 2 & 4; reading and writing operations on plurality of planes e.g., XA YA BA …).
Regarding claim 20, Tanizaki wherein each of the plurality of memory operation control related circuits comprises: a peripheral circuit configured to control a program operation and a read operation of a corresponding plane among a plurality of planes(FIG 2; 34); and a micro control unit configured to provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals FIG 2-3; 54 comprising 118 and 124 coupled to memory cell array 30), and configured to control an operation of the peripheral circuit in accordance with a result of decoding an instruction code corresponding to the peripheral circuit(FIG 4; col 7, line 5 – col 8 line 13; discloses 118 carry out address scramble of DRAM and address conversion being carried out by logic circuit e.g., 118 based on instructions codes e.g., FIG 4 shows the conversion).
Regarding claim 21, Tanizaki further comprising a divider circuit configured to divide a clock signal to generate the plurality of divided clock signals(FIG 2 & 14; col 9, lines 55-67 discloses 142 generated by multiplying frequency of internal dock signal 140(INT.CLK 20/4/8/100MHz) using PPL in memory).
Regarding claim 22, Tanizaki wherein the divider circuit is configured to generate the plurality of divided clock signals having a predetermined phase difference upon activation of a plane interleave read mode setting signal, and generate the plurality of divided clock signals having a same phase upon deactivation of the plane interleave read mode setting signal (FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phaser with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140).
Regarding claim 23, Tanizaki wherein the divider circuit comprises:a multi-phase signal generator configured to receive the clock signal to output multi-phase signals;a pre-divided clock generator configured to receive the multi-phase signals and the clock signal to output a plurality of pre-divided clock signals;an activation control circuit configured to selectively activate the pre- divided clock generator in response to a reset signal and a plurality of active signals corresponding to each of the plurality of memory regions(FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phaser with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140); and a plurality of multiplexers configured to selectively output the plurality of pre-divided clock signals as the plurality of divided clock signals in accordance with a plane interleave read mode setting signal (FIG 2; multiplexer 44(44 able to control on and off mode e.g., plurality functionalities providing control signals e.g., 64 60).
Regarding claim 24, Tanizaki further comprising an oscillator configured to generate the clock signal having a frequency corresponding to a number of the plurality of memory operation control related circuits (FIG 2 & 14; discloses internal frequency multiplied clock signal 142 is equal in phase with the internal clock signal 140 e.g., predetermined, and has a freq equal to or multiplied by an integer of internal clock signal 140 note internal frequency multiplied clock signal 142 is generated by multiplying the frequency of 140 using phase locked loop PLL e.g., oscillator is a key part inside PLL , PLL is feedback control system that uses an internal oscillator to match the frequency with internal clock signal).
).
Allowable Subject Matter
Claims 6-11 & 13-18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Byeon et al (US20120007624 FIG 4-5; discloses plurality of slave chips 200 and master chip 100, wherein 100 generates plurality of counter codes and clock distributing unit 152 generating driving clock by dividing frequency).
Suzuki et al (US4712211 FIG 1B & 12e; OR gate 830 outputting signal S20 having a wide high level durations in response to divided clock signal S17 S18).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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