Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 01/23/2025. These drawings are accepted.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over SPINNEY (US PAT No. 6426943 B1, hereinafter referred to as Spinney) in view of HERBST et al. (US PAT No. 6735679 B1, hereinafter referred to as HERBST).
Referring to claim 1, a network controller {“the [network] architecture is implemented in the BlazeFire.TM. chipset connected by the BlazeWire” (see Figs. 1 and 1a, Col 5, lines 35-37) including networks “(MII Octal MAC ASICs 10 and 20” (Col 5, lines 49-51) as well as other networks “local area Ethernets 63 or an interface for a wide area network such as the Distributed Access Device (DAD) WAN Processor 66 servicing T1 and POTS ("Plain Old Telephone Service") WAN lines 69 or for a Background Engine ("BE") 50.” (Col 5, lines 53-57)}, comprising:
a data check circuit {“The MOM chip handling the transmission of this packet will tag the outgoing packet”, see Fig. 1, Col 10, lines 49-51}, verifying whether a plurality of packets are valid {each of the packets comprising “field would contain the length which could be used for validity checks with length in the Layer 3 header”, see Figs. 1, 7a, 8a, Col 10, lines 61-63};
and an interrupt controller circuit {“insure that the BARK (the background engine kernel) can receive interrupts, for example, from [interrupt controller circuit] timers”, see Fig. 40, Col 26, lines 39-41};
Spinney does not appear to explicitly disclose a circuit counting according to a first packet in the plurality of packets to generate a first count value when the first packet is valid, and issuing an interrupt signal to a processor when the first count value is equal to a first predetermined value.
Herbst discloses a circuit counting {“ A Cell Counter Unit submodule is provided for keeping track of current cell counts for each egress”, see Fig. 20, Col 45, lines 29-30} according to a first packet {“submodule keeps track of the IP vector and the First Packet Pointer (FPP) and Next Packet Pointer (NPP).”, see Fig., Col 45, lines 3-5} in the plurality of packets to generate a first count value {“The Cell Counter Unit also generates status pins”, see Fig. 45, Col 45, lines 34-37} when the first packet is valid {“notify the remaining modules… the current [valid] status”, see Fig. 45, Col 45, lines 34-37}, and issuing an interrupt signal to a processor {said “Cell Counter” is a “principle function of this module is to make decisions for cells that come into PMMU 70” subcomponent (Col 42, lines 14-15), the “PMMU 70” which issues interrupt signal “HOL blocking mechanism” to a processor “appropriate ingress module of the appropriate [processors] GPIC 30 or EPIC 20”, see Fig. 20, Col 29, lines 23-25} when the first count value is equal to a first predetermined value {“programmed by CPU 52 to have a [predetermined value] high watermark and a [another predetermined value] low watermark per port per class of service (COS), with respect to buffer space within CBP 50”, see Fig. 20, Col 29, lines 15-17}.
Spinney and HERBST are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Spinney and HERBST before him or her, to modify Spinney’s “” incorporating HERBST’s “” (see Fig. 20, [0033]).
The suggestion/motivation for doing so would have been to implement a (BST [0002]).
Therefore, it would have been obvious to combine HERBST with Spinney to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Herbst discloses wherein the interrupt controller circuit further counts {“When the local cell count plus global cell count value…”, Col 30, lines 3-6} according to a clock signal {“counter is decremented every [according to a clock signal frequency] 32 clock cycles”, see Fig., Col 30, lines 5-7} to generate a second count value {“The Cell Counter Unit also generates status pins” (see Fig. 45, Col 45, lines 34-37) cells counting value depending on modes “Each port on each GPIC 30 and EPIC 20 is programmed” (Col 29, lines 14 and 15)}, and issues the interrupt signal to the processor {said “Cell Counter” is a “principle function of this module is to make decisions for cells that come into PMMU 70” subcomponent (Col 42, lines 14-15), the “PMMU 70” which issues interrupt signal “HOL blocking mechanism” to a processor “appropriate ingress module of the appropriate [processors] GPIC 30 or EPIC 20”, see Fig., Col 29, lines 23-25} when the second count value is equal to a second predetermined value {“programmed by CPU 52 to have a [predetermined value] high watermark and a [another predetermined value] low watermark per port per class of service (COS), with respect to buffer space within CBP 50”, see Fig., Col 29, lines 15-17}.
As per claim 3, the rejection of claim 2 is incorporated and Herbst discloses wherein if the plurality of packets are packets to be sent by a transmitter {“appropriate [processors] GPIC 30 or EPIC 20” (see Fig., Col 29, lines 23-25) having both ingress/egress bidirectional packet transferring “each EPIC 20 (as well as each GPIC 30) has an ingress submodule 14 and egress submodule 16, which provide port specific ingress and egress functions.” (see Figs. 8 and 9, Col 11, lines 52-55}, the clock signal is a clock signal used by the transmitter {“During the [a] second clock cycle Cn1, the second 16 bytes (16:31) of the currently transmitted data cell 112a are placed on the C channel 81 [by the transmitter” (see Fig., Col 13, lines 29-31) those “C channel” a part of “each GPIC module 30a and 30b would be granted access, followed by the EPIC modules, and finally the CMIC 40. After every arbitration time period the next I/O module with a valid request would be given access to the C channel 81” (Col 13, lines 4-7)}, and if the plurality of packets are packets to be received by a receiver {“packet slicing, and channel dispatching occurs in [receiver] ingress submodule 14.”, see Figs. 8 and 9, Col 11, lines 59-60}, the clock signal is a clock signal used by the receiver {“PMMU 70 is clocked using the SOC 10 core clock frequency, which can be 133 MHz in the example of the present embodiment” respective subcomponents including the receiver, see Fig. 20, Col 37, lines 35-37}.
As per claim 4, the rejection of claim 1 is incorporated and Herbst discloses further comprising:
a direct memory access (DMA) controller circuit {“Each DMA channel can therefore be programmed to perform a read or write DMA operation”, see Figs. 9 and 16, Col 34, lines 13-15}, comprising a buffer {“respect to buffer space within CBP 50”, see Fig. 20, Col 29, line 17}, the DMA controller circuit transfers data corresponding to the plurality of packets to the buffer {“output queue for a particular port hits the preprogrammed high watermark [plurality of packets] within the allocated buffer in CBP 50”, see Fig. 20, Col 29, lines 21-23} and generating an indicator signal {generating “COS queue status notification”, see Fig. 20, Col 29, lines 23-24} to indicate an amount of data to be processed in the buffer {“these registers can store data in terms of number of cells on the output queue, or in terms of number of packets on the output queue20”, see Fig. 20, Col 29, lines 47-49};
and a detection circuit {“to the appropriate ingress module of the [detection circuit] appropriate GPIC 30 or EPIC 20”, see Fig. 20, Col 29, lines 24-25}, determining according to the indicator signal whether a change rate {“with respect to budgeting [rate] of cells and packets”, see Fig. 20, Col 29, lines 54-55} of the amount of data to be processed exceeds a threshold {“global cell count for a particular egress port exceeds the HOL blocking marker register value,”, see Fig. 20, Col 29, lines 57-58} to generate a switching signal {“Depending upon the [switching signal] configuration and the packet length received for the egress port” (see Fig. 20, Col 30, lines 19-20) for the purpose “order maximize efficiency and switching speed” (Col 28, last line 67 through Col 29, line 1)};
wherein the interrupt controller circuit operates in a first mode {“each [GPIC] port will have appropriate buffer space allocated in the CBP to prevent port starvation [in a first mode],”, see Fig. 20, Col 30, lines 28-30} or a second mode according to the switching signal {“ensure that each [EPIC] port will be able to communicate with every other port to the extent that the network can support such [second mode] communication”, see Fig. 20, Col 30, lines 30-32}.
As per claim 5, the rejection of claim 4 is incorporated and Herbst discloses wherein when the change rate does not exceed the threshold {“Under these circumstances, the egresses and the ingresses could under-run [does not exceed the threshold]”, see Fig. 20, Col 58, lines 60-61}, the interrupt controller circuit operates in the first mode {“each [GPIC] port will have appropriate buffer space allocated in the CBP to prevent port starvation [in a first mode],”, see Fig. 20, Col 30, lines 28-30} according to the switching signal {“Depending upon the [switching signal] configuration and the packet length received for the egress port” (see Fig. 20, Col 30, lines 19-20) for the purpose “order maximize efficiency and switching speed” (Col 28, last line 67 through Col 29, line 1)} to generate the first count value {“programmed by CPU 52 to have a [predetermined value] high watermark and a [another predetermined value] low watermark per port per class of service (COS), with respect to buffer space within CBP 50”, see Fig. 20, Col 29, lines 15-17};
and when the change rate exceeds the threshold {“the egresses and the ingresses could… and overrun respectively [exceeds the threshold]”, see Fig. 20, Col 58, lines 60-61}, the interrupt controller circuit operates in the second mode {“ensure that each [EPIC] port will be able to communicate with every other port to the extent that the network can support such [second mode] communication”, see Fig. 20, Col 30, lines 30-32} according to the switching signal to generate the first count value and the second count value {“[first or second count value or both] The Cell Counter Unit also generates status pins” (see Fig. 45, Col 45, lines 34-37) cells counting value depending on modes “Each port on each GPIC 30 and EPIC 20 is programmed” (Col 29, lines 14 and 15)}.
As per claim 6, the rejection of claim 1 is incorporated and Herbst discloses wherein the interrupt controller circuit comprises:
a processing circuit {“Each egress manager 76”, see Fig. 12, Col 31, lines 39-40}, generating a first control signal {“selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67} according to sending/receiving information of the plurality of packets {“As data packets arrive in one or more of the COS priority queues of transaction FIFO 132”, see Fig. 13, Col 31, lines 61-62} and a switching signal having a first level {“Depending upon the [switching signal] configuration and the packet length received for the egress port” (see Fig. 20, Col 30, lines 19-20) for the purpose “order maximize efficiency and switching speed” (Col 28, last line 67 through Col 29, line 1)}, wherein the switching signal is generated by a detection circuit {“to the appropriate ingress module of the [detection circuit] appropriate GPIC 30 or EPIC 20”, see Fig. 20, Col 29, lines 24-25} according to a relation between a change rate {“with respect to budgeting [rate] of cells and packets”, see Fig. 20, Col 29, lines 54-55} of an amount of data to be processed in a buffer {“respect to buffer space within CBP 50”, see Fig. 20, Col 29, line 17} and a threshold {“global cell count for a particular egress port exceeds the HOL blocking marker register value,”, see Fig. 20, Col 29, lines 57-58};
a delay count circuit {“COS manager 133”, see Fig. 13, Col 32, lines 30-32}, generating the first count value {“programmed by CPU 52 to have a [predetermined value] high watermark and a [another predetermined value] low watermark per port per class of service (COS), with respect to buffer space within CBP 50”, see Fig. 20, Col 29, lines 15-17} according to the first control signal {“selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67}, and generating a first trigger signal according {“COS manager 133 can consider a [first trigger signal] maximum packet delay value”, see Fig. 13, Col 32, lines 30-32} to the first count value and the first predetermined value {“maximum packet delay value which must be met by a transaction FIFO queue”, see Fig. 13, Col 32, lines 30-32}, wherein the processor circuit further generates a second control signal {considering there are “priority COS queue are extracted from transaction FIFO 132” (Col 32, lines 13-15) provide a plurality of control signals to facilitate “selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67} according to the first trigger signal {“Utilizing a strict priority based scheduling method”, see Fig. 13, Col 32, lines 10-13};
and an interrupt signal generation circuit {“CMIC 40 supports buffering of four insert/delete messages which can be polled or interrupt driven”, see Figs. 13 and 16, Col 33, lines 58-60}, generating the interrupt signal according to the second control signal {issues interrupt signal “HOL blocking mechanism” to a processor “appropriate ingress module of the appropriate [processors] GPIC 30 or EPIC 20” (see Fig., Col 29, lines 23-25) according to a plurality of control signals to facilitate “selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13” (see Fig. 13, Col 31, lines 64-67)}.
As per claim 7, the rejection of claim 6 is incorporated and Herbst discloses wherein the interrupt controller circuit further comprises:
a timer circuit {“CLK represents the general clock signal presented to the logic circuitry within FIG. 31, and in particular, to the clock input of elements 101 and 102”, see Fig. 32, Col 38, lines 55-58}, generating a second count value according to a third control signal {“selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67} and a clock signal {“counter is decremented every [according to a clock signal frequency] 32 clock cycles”, see Fig., Col 30, lines 5-7}, and generating a second trigger signal {“COS manager 133 can consider a [respective trigger signal] maximum packet delay value”, see Fig. 13, Col 32, lines 30-32} according to the second count value {“The Cell Counter Unit also generates status pins” (see Fig. 45, Col 45, lines 34-37) cells counting value depending on modes “Each port on each GPIC 30 and EPIC 20 is programmed” (Col 29, lines 14 and 15)} and a second predetermined value {“programmed by CPU 52 to have a [predetermined value] high watermark and a [another predetermined value] low watermark per port per class of service (COS), with respect to buffer space within CBP 50”, see Fig. 20, Col 29, lines 15-17};
wherein, the processing circuit further generates the third control signal {“selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67} according to sending/receiving information {“As data packets arrive in one or more of the COS priority queues of transaction FIFO 132”, see Fig. 13, Col 31, lines 61-62} of the plurality of packets and the switching signal having a second level {“Depending upon the [switching signal] configuration and the packet length received for the egress port” (see Fig. 20, Col 30, lines 19-20) for the purpose “order maximize efficiency and switching speed” (Col 28, last line 67 through Col 29, line 1)}, and generates the second control signal {“selection of the packet pointer is based upon a [control signal(s)] queue scheduling algorithm, which is programmed by a user through CPU 52, within COS manager 13”, see Fig. 13, Col 31, lines 64-67} according to one of the first trigger signal {“COS manager 133 can consider a [first trigger signal] maximum packet delay value”, see Fig. 13, Col 32, lines 30-32} and the second trigger signal {“COS manager 133 can consider a [respective trigger signal] maximum packet delay value”, see Fig. 13, Col 32, lines 30-32}.
Referring to claims 8-11 are method claims reciting claim functionality to the apparatus claims 1-7, respectively, thereby rejected under the rationale as claims 1-7 recited above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “network controller”, “plurality of packets”, or “issuing an interrupt signal”: US 20250086129 A1, US 10067691 B1, US 20180253236 A1, US 9225672 B1, US 8995425 B1, US 20070253411 A1, AND US 7948976 B2.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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