Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 01/23/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 9 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, i.e. a hybrid switched-capacitor step-down DC-DC converter.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Appropriate correction is required.
Claim Objections
Claims 10-12 are objected to because of the following informalities: Regarding claim 10, in line 8, “the second capacitor of a q-th set” appears that it should read as “a second capacitor of a q-th set”;in line 9, “the fifth node of the q-th set” appears that it should read as “a fifth node of the q-th set”;in line 10, “q is 1 to P ,” appears that it should read as “q is 1 to P,”, because of an extra space before the comma (typo);in line 11, “the second node of the q-th set” appears that it should read as “a second node of the q-th set”.
Regarding claim 11, in line 8, “the second capacitor of a q-th set” appears that it should read as “a second capacitor of a q-th set”;in line 9, “the fifth node of the q-th set” appears that it should read as “a fifth node of the q-th set”;in line 11, “the second node of the q-th set” appears that it should read as “a second node of the q-th set”. Regarding claim 12, in line 8, “the second capacitor of a q-th set” appears that it should read as “a second capacitor of a q-th set”;in line 9, “the fifth node of the q-th set” appears that it should read as “a fifth node of the q-th set”;in line 11, “the second node of the q-th set” appears that it should read as “a second node of the q-th set”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (US Patent Application Publication US 2023/0179094 A1, hereinafter “Jin”).
Regarding claim 1, Jin discloses (see Fig. 1) a DC-DC converter circuit (power conversion circuit 1) comprising: a first capacitor (clamping capacitor C4), a second capacitor (second storage capacitor C2), a third capacitor (third storage capacitor C3), a first coil (second output inductor Lo2), a second coil (first output inductor Lo1), and a plurality of switches (M1, M2, M3, M4, M5, M6) (see [0018] “The clamping capacitor C4 is electrically connected between the third connection node C and the fifth connection node E”), wherein the plurality of switches are turned on and off to establish:
a first state in which the first capacitor is coupled between an input node (first terminal 121) and a first node (fifth connection node E), the second capacitor and the first coil are coupled in series between the first node and an output node (positive output terminal Vo+), the third capacitor and the second coil are coupled in series between the first node and the output node (see [0018] “The third storage capacitor C3 is electrically connected between the first connection node A and the fifth connection node E”), and a second node (second connection node B) to which the second capacitor and the first coil are coupled is coupled to a first reference potential node (negative output terminal Vo-) (see [0020] “The first grounding switch M5 is electrically connected between the second connection node B and the negative output terminal Vo-”), the first state being established when (see [0024] “the first switch M1 and the third switch M3 are turned on, and the second switch M2 and the fourth switch M4 are turned off”); and
a second state in which the second capacitor and the first coil are coupled in series between a third node (fourth connection node D) and the output node, the first capacitor, the third capacitor, and the second coil are coupled in series between the third node and the output node, a fourth node (second connection node B) to which the second capacitor and the first coil are coupled is coupled to a node (fifth connection node E) to which the first capacitor and the third capacitor are coupled, and a fifth node (first connection node A) to which the third capacitor and the second coil are coupled is coupled to a second reference potential node (negative output terminal Vo-) (see [0020] “the second grounding switch M6 is electrically connected between the first connection node A and the negative output terminal Vo-”), the second state being established when (see [0026] “the first switch M1 and the third switch M3 are turned off, and the second switch M2 and the fourth switch M4 are turned on”).
Regarding claim 2, Jin discloses (see Fig. 1) wherein the plurality of switches are turned on and off to establish a third state in which the first coil is coupled between the first reference potential node (negative output terminal Vo-, through the first grounding switch M5) and the output node, and the second coil is coupled between the second reference potential node (negative output terminal Vo-, through the second grounding switch M6) and the output node (see [0025] “During the period from time t0 to t1, which is a dead time, the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 are all turned off”).
Regarding claim 3, Jin discloses (see Fig. 1 and Fig. 2) wherein the plurality of switches are turned on and off such that the first state transitions to the third state, the third state transitions to the second state, the second state transitions to the third state, and the third state transitions to the first state (see Fig. 2, the period from 0 to t0 (first state) transitions to the dead time from t0 to t1 (third state), which transitions to the period from t1 to t2 (second state), which transitions to the dead time from t2 to t3 (third state), which transitions back to the first state).
Regarding claim 4, Jin discloses (see Fig. 1) wherein the plurality of switches include: a first switch (first switch M1) between the input node (first terminal 121) and the first capacitor (clamping capacitor C4); a second switch (second switch M2) between the first switch and the third node (fourth connection node D); a third switch (third switch M3) between the third node and the first node (fifth connection node E); a fourth switch (fourth switch M4) between the second node (second connection node B) and the first node; a fifth switch (first grounding switch M5) between the second node and the first reference potential node (negative output terminal Vo-); and a sixth switch (second grounding switch M6) between the fifth node (first connection node A) and the second reference potential node (negative output terminal Vo-) (see [0017] “The first switch M1 and the second switch M2 are electrically connected in series to form a third connection node C. The second switch M2 and the third switch M3 are electrically connected in series to form a fourth connection node D. The third switch M3 and the fourth switch M4 are electrically connected in series to form a fifth connection node E”).
Regarding claim 5, Jin discloses (see Fig. 1) wherein the plurality of switches include the first through sixth switches (first switch M1, second switch M2, third switch M3, fourth switch M4, first grounding switch M5, and second grounding switch M6) arranged as set forth above with respect to claim 4 (see [0020] “The first grounding switch M5 is electrically connected between the second connection node B and the negative output terminal Vo-, and the second grounding switch M6 is electrically connected between the first connection node A and the negative output terminal Vo-”).
Regarding claim 6, Jin discloses (see Fig. 1) wherein the plurality of switches include the first through sixth switches (first switch M1, second switch M2, third switch M3, fourth switch M4, first grounding switch M5, and second grounding switch M6) arranged as set forth above with respect to claim 4 (see [0017] “The switch bridge arm 124 includes n+1 switches (M1, M2, M3, M4)”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Das et al. (US Patent Application Publication US 2020/0212795 A1, hereinafter “Das”).
Regarding claim 7, Jin discloses (see Fig. 1) a DC-DC converter circuit (power conversion circuit 1) comprising: a first capacitor (clamping capacitor C4); a capacitor set including a second capacitor (second storage capacitor C2) and a third capacitor (third storage capacitor C3) (see [0018] “The second storage capacitor C2 is electrically connected between the second connection node B and the fourth connection node D”); a first coil (second output inductor Lo2); a second coil (first output inductor Lo1); and a plurality of switches (M1, M2, M3, M4, M5, M6), wherein the plurality of switches are turned on and off to establish a first state in which the first capacitor is coupled between an input node (first terminal 121) and a first node (fifth connection node E), the second capacitor of the capacitor set and the first coil are coupled in series between the first node and an output node (positive output terminal Vo+), and the third capacitor of the capacitor set and the second coil are coupled in series between the first node and the output node (see [0024] “the first switch M1 and the third switch M3 are turned on, and the second switch M2 and the fourth switch M4 are turned off”), and a second state in which the second capacitor of the capacitor set and the first coil are coupled in series between a fourth node (second connection node B) and the output node, and the first capacitor, the third capacitor of the capacitor set, and the second coil are coupled in series between the fourth node and the output node (see [0026] “the first switch M1 and the third switch M3 are turned off, and the second switch M2 and the fourth switch M4 are turned on”).
Jin does not disclose first to P-th capacitor sets (P is an integer of 2 or more) each including a second capacitor and a third capacitor, the second capacitors of the first to P-th capacitor sets and the first coil being coupled in series, and the third capacitors of the first to P-th capacitor sets and the second coil being coupled in series.
However, Das teaches (see Fig. 34) first to P-th capacitor sets (P is an integer of 2 or more) each including a second capacitor and a third capacitor, in which a plurality of switched-capacitor networks (each switched-capacitor network corresponding to a capacitor set) are cascaded and coupled to a common inductive network (the first coil and the second coil) (see [0049] “FIG. 34 illustrates an extended version of a DC-DC converter architecture where a plurality of switched capacitor networks are cascaded on top of each other and a common inductive network”), Das being directed to the same dual-inductor hybrid converter (see [0061] “this converter and its other versions are called dual-inductor hybrid converter (DIHC)”), and Das further disclosing that such an expanded converter uses (N-1) capacitors to provide N levels (see [0074] “Both FIG. 5 and FIG. 6 illustrate a dual-inductor hybrid converter (DIHC) that uses (N-1) capacitors and has N levels”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter circuit of Jin to include first to P-th capacitor sets (P is an integer of 2 or more) each including a second capacitor and a third capacitor, as taught by Das, because increasing the number of capacitor sets increases the number of levels of the switched-capacitor network to block most of the input voltage and generate a lower level output voltage (see [0011] of Das), thereby achieving a larger voltage conversion ratio; and further because Jin itself teaches that the number of storage capacitors may be increased (see [0041] of Jin “the number of the storage capacitors of the power conversion circuit is not limited to three and may be any integer greater than 1”).
Regarding claim 8, Jin discloses (see Fig. 1) wherein the plurality of switches are turned on and off to establish a third state in which the first coil is coupled between the first reference potential node (negative output terminal Vo-, through the first grounding switch M5) and the output node, and the second coil is coupled between the second reference potential node (negative output terminal Vo-, through the second grounding switch M6) and the output node (see [0025] “During the period from time t0 to t1, which is a dead time, the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 are all turned off”).
Regarding claim 9, Jin discloses (see Fig. 1 and Fig. 2) wherein the plurality of switches are turned on and off such that the first state transitions to the third state, the third state transitions to the second state, the second state transitions to the third state, and the third state transitions to the first state (see Fig. 2, illustrating the periodic sequencing among the first state, the dead-time third state, and the second state).
Regarding claim 10, Jin discloses (see Fig. 1) wherein the plurality of switches include a first switch (first switch M1) between the input node (first terminal 121) and the first capacitor (clamping capacitor C4); a second switch (second switch M2) between the first switch and a fourth node (second connection node B); a third switch (third switch M3) and a fourth switch (fourth switch M4) associated with the capacitor set; a fifth switch (first grounding switch M5) coupled to the first reference potential node (negative output terminal Vo-); and a sixth switch (second grounding switch M6) coupled to the second reference potential node (negative output terminal Vo-) (see [0017] “The second switch M2 and the third switch M3 are electrically connected in series to form a fourth connection node D. The third switch M3 and the fourth switch M4 are electrically connected in series to form a fifth connection node E”).
Jin does not disclose, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets.
However, Das teaches (see Fig. 34) a plurality of cascaded switched-capacitor networks, each switched-capacitor network including its own switches, such that a third switch and a fourth switch are provided for each of the first to P-th capacitor sets (see [0049] “FIG. 34 illustrates an extended version of a DC-DC converter architecture where a plurality of switched capacitor networks are cascaded on top of each other and a common inductive network”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter circuit of Jin to include, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets, as taught by Das, because providing the switches of each cascaded switched-capacitor network permits the converter to be expanded to a plurality of capacitor sets to achieve a larger voltage conversion ratio, consistent with Jin’s teaching that the number of storage capacitors may be any integer greater than 1 (see [0041] of Jin “the number of the storage capacitors of the power conversion circuit is not limited to three and may be any integer greater than 1”).
Regarding claim 11, Jin discloses (see Fig. 1) wherein the plurality of switches include a first switch (first switch M1) between the input node (first terminal 121) and the first capacitor (clamping capacitor C4); a second switch (second switch M2) between the first switch and a fourth node (second connection node B); a third switch (third switch M3) and a fourth switch (fourth switch M4) associated with the capacitor set; a fifth switch (first grounding switch M5) coupled to the first reference potential node (negative output terminal Vo-); and a sixth switch (second grounding switch M6) coupled to the second reference potential node (negative output terminal Vo-) (see [0017] “The second switch M2 and the third switch M3 are electrically connected in series to form a fourth connection node D. The third switch M3 and the fourth switch M4 are electrically connected in series to form a fifth connection node E”).
Jin does not disclose, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets.
However, Das teaches (see Fig. 34) a plurality of cascaded switched-capacitor networks, each switched-capacitor network including its own switches, such that a third switch and a fourth switch are provided for each of the first to P-th capacitor sets (see [0049] “FIG. 34 illustrates an extended version of a DC-DC converter architecture where a plurality of switched capacitor networks are cascaded on top of each other and a common inductive network”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter circuit of Jin to include, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets, as taught by Das, because providing the switches of each cascaded switched-capacitor network permits the converter to be expanded to a plurality of capacitor sets to achieve a larger voltage conversion ratio, consistent with Jin’s teaching that the number of storage capacitors may be any integer greater than 1 (see [0041] of Jin “the number of the storage capacitors of the power conversion circuit is not limited to three and may be any integer greater than 1”).
Regarding claim 12, Jin discloses (see Fig. 1) wherein the plurality of switches include a first switch (first switch M1) between the input node (first terminal 121) and the first capacitor (clamping capacitor C4); a second switch (second switch M2) between the first switch and a fourth node (second connection node B); a third switch (third switch M3) and a fourth switch (fourth switch M4) associated with the capacitor set; a fifth switch (first grounding switch M5) coupled to the first reference potential node (negative output terminal Vo-); and a sixth switch (second grounding switch M6) coupled to the second reference potential node (negative output terminal Vo-) (see [0017] “The second switch M2 and the third switch M3 are electrically connected in series to form a fourth connection node D. The third switch M3 and the fourth switch M4 are electrically connected in series to form a fifth connection node E”).
Jin does not disclose, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets.
However, Das teaches (see Fig. 34) a plurality of cascaded switched-capacitor networks, each switched-capacitor network including its own switches, such that a third switch and a fourth switch are provided for each of the first to P-th capacitor sets (see [0049] of Das “FIG. 34 illustrates an extended version of a DC-DC converter architecture where a plurality of switched capacitor networks are cascaded on top of each other and a common inductive network”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the DC-DC converter circuit of Jin to include, in each case where q is 1 to P, a third switch and a fourth switch for each of the first to P-th capacitor sets, as taught by Das, because providing the switches of each cascaded switched-capacitor network permits the converter to be expanded to a plurality of capacitor sets to achieve a larger voltage conversion ratio, consistent with Jin’s teaching that the number of storage capacitors may be any integer greater than 1 (see [0041] of Jin “the number of the storage capacitors of the power conversion circuit is not limited to three and may be any integer greater than 1”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0231601 A1 discloses a multi-phase hybrid converter with a flying capacitor and output inductor pair. US 2023/0387804 A1 discloses a hybrid converter with switched capacitors and an output inductor pair. US 12,081,111 B2 discloses a high voltage gain bi-directional DC voltage converter with switched capacitors and an inductor pair.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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