DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
1. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “configured to” in claims 1-8 and “means” in claim 9.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-2, 4-11, 13-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Das Sharma (Pub. No. US20220334995)
As per claims 1, 9, 10, 17, Das Sharma discloses a processor-based device, comprising:
a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module (paragraph 78, lines 1-2, UCIe protocol stacks) configured to: determine, during a first initialization of the processor-based device, that the UCIe x64 module supports Flexible Link Width (FLW) (paragraph 46, lines 4-5, scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider);
responsive to determining that the UCIe x64 module supports FLW, determine, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively (paragraph 46, lines 4-5, scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider); and
responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module: establish the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes (paragraph 78, UCIe protocol stacks, where different numbers of PHY modules are utilized to implement the respective physical layer of the UCIe protocol stack, a single module 1205 is used to connect to the D2D adapter 1010 implement the physical layer of the port. The physical layer constructed using 4 modules 1205a-d to further scale the bandwidth of the link (e.g., by providing four x64 data lane groupings in each of the 4 modules to form a x320 data width);
establish the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes (paragraph 78, Each module 1205a-b has its own logical PHY (e.g., 1105a,b), set of sideband lanes (e.g., 1110a,b), and set of mainband lanes (e.g., 1115a,b). The use of two modules 1205a-b effectively doubles the bandwidth of the link as compared to implementations using only a single module); and
establish data transfer via the first x32 link and the second x32 link (paragraph 46, lines 5-6, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider).
As per claims 2, 11, 18, Das Sharma discloses wherein the UCIe x64 module is configured to determine that the UCIe x64 module supports FLW by being configured to determine that either one of a first FLW module configuration bit in a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device and a second FLW module configuration bit in a physical layer (PHY) control register of the processor-based device is set (paragraph 88, independent registers (e.g., dedicated vendor-specific extended capabilities (DVSEC) registers) may be defined for the D2D adapter and PHY of a port (and software is permitted to use the presence of these independent registers to identify a device as being UCIe)).
As per claims 4, 13, 20, Das Sharma discloses wherein the UCIe x64 module is further configured to, subsequent to determining that the first UCIe x32 module and the second UCIe x32 module require the first x32 link and the second x32 link, respectively:
update a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device to indicate a count of active modules, a configuration of each active module, and a count of die-to-die stacks required to support links between the UCIe x64 module and the first and second UCIe x32 modules (paragraph 61, lines 13-16, enable the interconnection of different devices from different vendors and different fabs across different technology nodes using different packaging choices); and
configure a first die-to-die stack and a second die-to-die stack corresponding to the first UCIe x32 module and the second UCIe x32 module, respectively (paragraph 40, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address).
As per claims 5, 14 Das Sharma discloses wherein: the UCIe x64 module comprises a Raw Die-to-Die Interface (RDI) multiplexor (paragraph 56, line 2, CXL arbitration/multiplexing (ARB/MUX) logic 520) configured to arbitrate data transmitted via the first and the second x32 links (paragraph 56, lines 12-16, PCIe mode or CXL mode based on results of alternate mode negotiation during the link training process. In some implementations, the physical layer may support multiple signaling rates (e.g., 8 GT/s, 16 GT/s, 32 GT/s, etc.) and multiple link widths (e.g., x16, x8, x4, x2, x1, etc.)); and
the UCIe x64 module is configured to establish the data transfer via the first x32 link and the second x32 link using the RDI multiplexor links (paragraph 56, lines 12-16, PCIe mode or CXL mode based on results of alternate mode negotiation during the link training process. In some implementations, the physical layer may support multiple signaling rates (e.g., 8 GT/s, 16 GT/s, 32 GT/s, etc.) and multiple link widths (e.g., x16, x8, x4, x2, x1, etc.)).
As per claims 6, 15, Das Sharma discloses wherein the UCIe x64 module is further configured to:
determine, during a second initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x32 module that requires a third x32 link (paragraph 46, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider); and
responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x32 module: establish the third x32 link with the single UCIe x32 module using the plurality of mainband transmit signal lanes including the first 32 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including the first 32 bits of the mainband data receive signal lane, and the plurality of sideband signal lanes(paragraph 78, Each module 1205a-b has its own logical PHY (e.g., 1105a,b), set of sideband lanes (e.g., 1110a,b), and set of mainband lanes (e.g., 1115a,b). The use of two modules 1205a-b effectively doubles the bandwidth of the link as compared to implementations using only a single module); and
establish data transfer via the third x32 link (paragraph 46, lines 5-6, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider).
As per claims 7, 16, Das Sharma discloses wherein the UCIe x64 module is further configured to: determine, during a third initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x64 module that requires an x64 link(paragraph 46, lines 5-6, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider); and
responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x64 module: establish the x64 link with the single UCIe x64 module using the plurality of mainband transmit signal lanes including all 64 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including all 64 bits of the mainband data receive signal lane, the plurality of sideband signal lanes, the plurality of redundant mainband transmit signal lanes, the plurality of redundant mainband receive signal lanes, and the plurality of redundant sideband signal lanes(paragraph 78, Each module 1205a-b has its own logical PHY (e.g., 1105a,b), set of sideband lanes (e.g., 1110a,b), and set of mainband lanes (e.g., 1115a,b). The use of two modules 1205a-b effectively doubles the bandwidth of the link as compared to implementations using only a single module); and
establish data transfer via the x64 link (paragraph 46, lines 5-6, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider).
As per claim 8, Das Sharma discloses integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (paragraph 4, line 3, smartphones).
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 3, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (Pub. No. US20220334995) in view of Dakshinamurthy et al. (Pub. No. US20240095206)
Das Sharma discloses all the limitations as the above but does not explicitly disclose wherein the UCIe x64 module is further configured to, responsive to determining that the UCIe x64 module supports FLW, set an FLW indication of an MBINIT.PARAM message. However, Dakshinamurthy discloses this (paragraph 61, sequence for parameter exchange: (1) the UCIe Module sends sideband message {MBINIT.PARAM configuration req} to exchange parameters with the UCIe Module Partner)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Dakshinamurthy with the teaching of Das Sharma so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Muthrasanallur et al. [Pub. No. US 20240345983] discloses a MB link connection may be configured to include a main data path of the UCIe link.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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