DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10, and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Calhoun et al (Pub 2015/0214894, further referred to as Calhoun).
As to claim 1, Calhoun teaches a crystal oscillator (fig 1-3) comprising:
a crystal (106, paragraph 27);
an inverter (301, paragraphs 2932 and 33) having an input connected to a first terminal of the crystal (XI) and an output connected to a second terminal (Xo) of the crystal, the inverter including an n-type metal oxide semiconductor transistor (301 has an NMOS) and a p-type metal oxide semiconductor transistor (301 has a PMOS) configured to invert an input oscillation signal from the crystal (paragraph 27); and
a back gate bias control circuit (202/303) configured to adjust a negative resistance of the inverter (paragraphs 29 and 32) by controlling a body bias (paragraphs 32 and 33, changing the negative resistance is body biasing the transistor) of at least one of the n-type metal oxide semiconductor transistors or the p-type metal oxide semiconductor transistor.
As to claim 2, Calhoun teaches controls a body bias of both the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor (fig 3, control signal is sent to both transistors).
As to claim 3, Calhoun teaches wherein the back gate bias control circuit sets the back gate bias to a first level during startup of the crystal oscillator and to a second level during steady state operation of the crystal oscillator (fig 13, paragraph 46).
As to claim 10, Calhoun wherein a source of the p-type metal oxide semiconductor transistor is connected to a reference voltage, a gate of the p-type metal oxide semiconductor transistor is connected to an input of the inverter, a drain of the p-type metal oxide semiconductor transistor is connected to an output of the inverter, a source of the n-type metal oxide semiconductor transistor is connected to a ground voltage, a gate of the n-type metal oxide semiconductor transistor is connected to the input of the inverter, and a drain of the n-type metal oxide semiconductor transistor is connected to the output of the inverter (fig 3, the inverter is formed as standard CMOS inverter between a reference voltage and ground).
As to claim 12, Calhoun teaches a method of generating an oscillation signal using a crystal oscillator (fig 1-3) comprising:
Receiving an input oscillation signal from a crystal (106, paragraph 27) as an input to an inverter;
inverting using an inverter (301, paragraphs 2932 and 33) having an input connected to a first terminal of the crystal (XI) and an output connected to a second terminal (Xo) of the crystal, the inverter including an n-type metal oxide semiconductor transistor (301 has an NMOS) and a p-type metal oxide semiconductor transistor (301 has a PMOS) configured to invert an input oscillation signal from the crystal (paragraph 27); and
adjusting a negative resistance of the inverter ((202/303) paragraphs 29 and 32) by controlling a body bias (paragraphs 32 and 33, changing the negative resistance is body biasing the transistor) of at least one of the n-type metal oxide semiconductor transistors or the p-type metal oxide semiconductor transistor.
As to claim 13, Calhoun teaches controls a body bias of both the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor (fig 3, control signal is sent to both transistors).
As to claim 14, Calhoun teaches wherein the back gate bias control circuit sets the back gate bias to a first level during startup of the crystal oscillator and to a second level during steady state operation of the crystal oscillator (fig 13, paragraph 46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Calhoun.
As to claim 17, Calhoun teaches a crystal oscillator (fig 1-3) comprising:
a crystal (106, paragraph 27);
an inverter (301, paragraphs 2932 and 33) having an input connected to a first terminal of the crystal (XI) and an output connected to a second terminal (Xo) of the crystal, the inverter including an n-type metal oxide semiconductor transistor (301 has an NMOS) and a p-type metal oxide semiconductor transistor (301 has a PMOS) configured to invert an input oscillation signal from the crystal (paragraph 27); and
a back gate bias control circuit (202/303) configured to adjust a negative resistance of the inverter (paragraphs 29 and 32) by controlling a body bias (paragraphs 32 and 33, changing the negative resistance is body biasing the transistor) of at least one of the n-type metal oxide semiconductor transistors or the p-type metal oxide semiconductor transistor.
Calhoun does not explicitly teach using a phase locked loop with the crystal oscillator.
As would have been recognized by a person of ordinary skill in the art using a phase locked loop with a crystal oscillator is done merely as intended use with user desired circuitry (crystal oscillators are notoriously well known in the art for generating reference signals and used with PLL circuits). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to use the crystal oscillator taught in Calhoun with a PLL as doing so would be mere matter of intended use to use the crystal oscillator with user desired circuitry.
As to claim 18, Calhoun teaches controls a body bias of both the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor (fig 3, control signal is sent to both transistors).
As to claim 19, Calhoun teaches wherein the back gate bias control circuit sets the back gate bias to a first level during startup of the crystal oscillator and to a second level during steady state operation of the crystal oscillator (fig 13, paragraph 46).
Allowable Subject Matter
Claims 4-9, 11, 15, 16, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teach or suggest a first controllable source and first body resistor as is recited in claims 4-7; the reference voltage further adjusting the negative resistance as is recited in claims 8, 9, 15-16 and 20; and the first and second feedback resistors with switching recited in claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ahmed (Pub 2020/0204115) teaches a body biasing to a transistor of an amplifier in a crystal oscillator. Nasu (Pub 2010/0482094) teaches generating a gate biasing to a inverter amplifier of a crystal oscillator.
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/JEFFREY M SHIN/Primary Examiner, Art Unit 2849