Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 01/23/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities: Regarding claim 3, in lines 6-7, “a second input of the amplifier is coupled between the transistor and the first resistor” appears that it should read as “a second input of the amplifier is coupled to a node between the transistor and the first resistor”, because an input of the amplifier is a single node and cannot be connected in series between two circuit elements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (US Patent US 9,791,874 B1).
Regarding claim 1, Wang discloses (see Fig. 4) a voltage regulator (voltage regulator 400) comprising: a voltage circuit configured to generate a gate voltage based on a reference voltage (the voltage circuit comprising differential amplifier 410, output transistor MN 402, and resistors Rfb2 and Rfb1 generates the gate voltage vgate 405 from the reference voltage Vref 408; see col. 5, lines 55-59 of Wang, “The voltage controller 410 is coupled to receive the reference voltage 408 and the feedback path voltage Vfb 404 from the output transistor 402 from the voltage divider Rfb2 and Rfb1, and in response adjust the vgate control voltage 405”); an n-type field effect transistor (NFET) (NMOS MNsense), wherein a gate of the NFET is coupled to the voltage circuit to receive the gate voltage (the gate of MNsense is coupled to the output of differential amplifier 410 and receives the vgate control voltage 405; see col. 6, lines 5-6 of Wang, “The amplifier control circuit 414 is configured to sense the control voltage 405 sent to the output transistor 402”), and a source of the NFET is coupled to an output of the voltage regulator (the source of MNsense is coupled to the regulated voltage output port/terminal 420; see col. 6, lines 1-4 of Wang, “an amplifier control circuit 414 and an amplified current circuit 416 each coupled in parallel between the power supply input 418 and the regulated voltage output 420”); a current source coupled between a supply rail and a drain of the NFET (PMOS MPsns is coupled between the power supply input port/terminal 418 and the drain of MNsense; see col. 6, lines 11-12 of Wang, “the amplifier control circuit 414 includes a first PMOS MPsns coupled in series with an NMOS MNsense”); and a p-type field effect transistor (PFET) (PMOS MPsnso), wherein a source of the PFET is coupled to the supply rail (the source of MPsnso is coupled to the power supply input port/terminal 418), a gate of the PFET is coupled to the drain of the NFET (the gate of MPsnso is coupled to the commonly connected gate and drain of the diode-connected MPsns, which is the drain of MNsense; see col. 6, lines 15-17 of Wang, “The first PMOS MPsns and the second PMOS MPsnso are configured as a current mirror”), and a drain of the PFET is coupled to the output of the voltage regulator (the drain of MPsnso is coupled to the regulated voltage output port/terminal 420).
Regarding claim 2, Wang discloses (see Fig. 4) further comprising a resistor coupled between the source of the NFET and a low rail (resistor Rfb2 is coupled between the source of MNsense, which is the regulated voltage output port/terminal 420, and ground through resistor Rfb1).
Regarding claim 3, Wang discloses (see Fig. 4) wherein the voltage circuit comprises: a first resistor (resistor Rfb1); a transistor coupled between the supply rail and the first resistor (output transistor MN 402 is coupled between the power supply input port/terminal 418 and resistor Rfb1 through resistor Rfb2), wherein a gate of the transistor is coupled to the gate of the NFET (the control input 403 of MN 402 and the gate of MNsense are both coupled to the vgate control voltage 405); and an amplifier (differential amplifier 410), wherein a first input of the amplifier is configured to receive the reference voltage (the non-inverting input of differential amplifier 410 receives the reference voltage Vref 408), a second input of the amplifier is coupled between the transistor and the first resistor via a feedback path (the inverting input of differential amplifier 410 is coupled to the node between resistor Rfb2 and resistor Rfb1 through the feedback path 404 carrying the voltage Vfb), and an output of the amplifier is coupled to the gate of the transistor (the output of differential amplifier 410 is coupled to the control input 403 of MN 402; see col. 5, lines 51-54 of Wang, “the output transistor 402 is configured to provide a first current from the power supply input 418 to the regulated voltage output 420 based on the vgate control voltage 405 received from the voltage controller 410”).
Regarding claim 4, Wang discloses (see Fig. 4) wherein the first resistor is coupled between the transistor and a low rail (resistor Rfb1 is coupled between output transistor MN 402 and ground, resistor Rfb2 being connected between the source of MN 402 and resistor Rfb1).
Regarding claim 5, Wang discloses (see Fig. 4) further comprising a second resistor coupled between the source of the NFET and the low rail (resistor Rfb2 is coupled between the source of MNsense, which is the regulated voltage output port/terminal 420, and ground through resistor Rfb1).
Regarding claim 6, Wang discloses (see Fig. 4) wherein a drain of the transistor is coupled to the supply rail (the drain of MN 402 is coupled to the power supply input port/terminal 418; see col. 1, lines 23-26 of Wang, “the output transistor is an NMOS transistor having a drain coupled to the power supply input, a source coupled to the regulated voltage output, and a gate coupled to receive the control voltage”), and the second input of the amplifier is coupled to a source of the transistor via the feedback path (the inverting input of differential amplifier 410 is coupled to the source of MN 402 through resistor Rfb2 and the feedback path 404 carrying the voltage Vfb).
Regarding claim 7, Wang discloses (see Fig. 4) wherein the first resistor is coupled between the source of the transistor and a low rail (resistor Rfb1 is coupled between the source of MN 402 and ground, resistor Rfb2 being connected between the source of MN 402 and resistor Rfb1).
Regarding claim 8, Wang discloses (see Fig. 4) further comprising a second resistor coupled between the source of the NFET and the low rail (resistor Rfb2 is coupled between the source of MNsense, which is the regulated voltage output port/terminal 420, and ground through resistor Rfb1).
Regarding claim 9, Wang discloses (see Fig. 4) a voltage regulator (voltage regulator 400), comprising: a first n-type field effect transistor (NFET) (output transistor MN 402), wherein a drain of the first NFET is coupled to a supply rail (the drain of MN 402 is coupled to the power supply input port/terminal 418; see col. 1, lines 23-26 of Wang, “the output transistor is an NMOS transistor having a drain coupled to the power supply input, a source coupled to the regulated voltage output, and a gate coupled to receive the control voltage”); a first resistor coupled between a source of the first NFET and a low rail (resistor Rfb1 is coupled between the source of MN 402 and ground, resistor Rfb2 being connected between the source of MN 402 and resistor Rfb1); an amplifier (differential amplifier 410), wherein a first input of the amplifier is configured to receive a reference voltage (the non-inverting input of differential amplifier 410 receives the reference voltage Vref 408), a second input of the amplifier is coupled to the source of the first NFET via a feedback path (the inverting input of differential amplifier 410 is coupled to the source of MN 402 through resistor Rfb2 and the feedback path 404 carrying the voltage Vfb), and an output of the amplifier is coupled to a gate of the first NFET (the output of differential amplifier 410 is coupled to the control input 403 of MN 402 and delivers the vgate control voltage 405); a second NFET (NMOS MNsense), wherein a gate of the second NFET is coupled to the gate of the first NFET (the gate of MNsense and the control input 403 of MN 402 are both coupled to the vgate control voltage 405; see col. 6, lines 5-6 of Wang, “The amplifier control circuit 414 is configured to sense the control voltage 405 sent to the output transistor 402”), and a source of the second NFET is coupled to an output of the voltage regulator (the source of MNsense is coupled to the regulated voltage output port/terminal 420; see col. 6, lines 1-4 of Wang, “an amplifier control circuit 414 and an amplified current circuit 416 each coupled in parallel between the power supply input 418 and the regulated voltage output 420”); a current source coupled between the supply rail and a drain of the second NFET (PMOS MPsns is coupled between the power supply input port/terminal 418 and the drain of MNsense; see col. 6, lines 11-12 of Wang, “the amplifier control circuit 414 includes a first PMOS MPsns coupled in series with an NMOS MNsense”); and a p-type field effect transistor (PFET) (PMOS MPsnso), wherein a source of the PFET is coupled to the supply rail (the source of MPsnso is coupled to the power supply input port/terminal 418), a gate of the PFET is coupled to the drain of the second NFET (the gate of MPsnso is coupled to the commonly connected gate and drain of the diode-connected MPsns, which is the drain of MNsense; see col. 6, lines 15-17 of Wang, “The first PMOS MPsns and the second PMOS MPsnso are configured as a current mirror”), and a drain of the PFET is coupled to the output of the voltage regulator (the drain of MPsnso is coupled to the regulated voltage output port/terminal 420).
Regarding claim 10, Wang discloses (see Fig. 4) further comprising a second resistor coupled between the source of the second NFET and the low rail (resistor Rfb2 is coupled between the source of MNsense, which is the regulated voltage output port/terminal 420, and ground through resistor Rfb1).
Regarding claim 13, Wang discloses (see Fig. 4) a method for operating a voltage regulator (voltage regulator 400), the voltage regulator including an n-type field effect transistor (NFET) (NMOS MNsense) and a p-type field effect transistor (PFET) (PMOS MPsnso), wherein a source of the NFET is coupled to an output of the voltage regulator (the source of MNsense is coupled to the regulated voltage output port/terminal 420; see col. 6, lines 1-4 of Wang, “an amplifier control circuit 414 and an amplified current circuit 416 each coupled in parallel between the power supply input 418 and the regulated voltage output 420”), a source of the PFET is coupled to a supply rail (the source of MPsnso is coupled to the power supply input port/terminal 418), a gate of the PFET is coupled to a drain of the NFET (the gate of MPsnso is coupled to the commonly connected gate and drain of the diode-connected MPsns, which is the drain of MNsense; see col. 6, lines 15-17 of Wang, “The first PMOS MPsns and the second PMOS MPsnso are configured as a current mirror”), and a drain of the PFET is coupled to the output of the voltage regulator (the drain of MPsnso is coupled to the regulated voltage output port/terminal 420), the method comprising: generating a gate voltage based on a reference voltage (differential amplifier 410 generates the vgate control voltage 405 from the reference voltage Vref 408); applying the gate voltage to a gate of the NFET (the vgate control voltage 405 is applied to the gate of MNsense); and providing a bias current to the drain of the NFET (PMOS MPsns of the amplifier control circuit 414 supplies current from the power supply input port/terminal 418 to the drain of MNsense; see col. 6, lines 6-7 of Wang, “in response directly supply a first portion of the second current”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Geynet et al. (US Patent US 7,859,240 B1, hereinafter “Geynet”).
Regarding claim 11, Wang does not disclose wherein a channel width of the second NFET is larger than a channel width of the first NFET.
However, Geynet teaches (see Fig. 2) wherein a channel width of the second NFET is larger than a channel width of the first NFET (the output leg 210 of the replica type voltage regulator 200 includes a second larger transistor 216 connected as a source follower, having a source coupled to the output node 204 of the voltage regulator 200 and a gate controlled by the gate node Vgate of a first transistor 212 that is connected as a source follower in the reference leg 206 and has an output node Vsource coupled to ground 208 through a series resistor network 214; see col. 4, lines 53-59 of Geynet, “a first transistor 212 connected as a source follower (SF) and including a gate node (Vgate) coupled to and controlled by an operational amplifier (OPAMP) or a charge pump and an output node (Vsource) coupled to ground 208 through a series resistor network 214”, and see col. 4, lines 58-62 of Geynet, “The output leg 210 includes a second larger transistor 216, also connected as a source follower and controlled by the gate node (Vgate) of the first transistor 212”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator of Wang wherein a channel width of the second NFET is larger than a channel width of the first NFET, as taught by Geynet, because it can help the second NFET provide a desired load current at the output of the voltage regulator while the first NFET establishes the target voltage in the branch coupled to the amplifier (see col. 1, lines 29-34 of Geynet, “In a replica voltage regulator a voltage established in one portion or one leg of a circuit is replicated in another leg or portion of the circuit, typically by larger sized devices, to provide a desired load or output voltage”).
Regarding claim 12, Wang does not disclose wherein the channel width of the second NFET is at least twice as large as the channel width of the first NFET.
However, Geynet teaches (see Fig. 2) the general condition in which the transistor of the output leg is larger than the transistor of the reference leg (the output leg 210 includes a second larger transistor 216 connected as a source follower and controlled by the gate node Vgate of the first transistor 212 of the reference leg 206; see col. 4, lines 58-62 of Geynet, “The output leg 210 includes a second larger transistor 216, also connected as a source follower and controlled by the gate node (Vgate) of the first transistor 212”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator of Wang wherein the channel width of the second NFET is at least twice as large as the channel width of the first NFET, as taught by the general condition of Geynet, because it can help the second NFET provide at least twice the load current of the first NFET at the output of the voltage regulator, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Fort (US Patent Application Publication US 2021/0124384 A1).
Regarding claim 14, Wang discloses (see Fig. 4) wherein the voltage regulator further comprises a transistor (output transistor MN 402), and wherein generating the gate voltage based on the reference voltage comprises: applying the gate voltage to a gate of the transistor (the vgate control voltage 405 is applied to the control input 403 of MN 402).
Wang does not disclose sensing a voltage at a source of the transistor; and adjusting the gate voltage in a direction that reduces a difference between the voltage at the source of the transistor and the reference voltage.
However, Fort teaches (see Fig. 4) sensing a voltage at a source of the transistor (the source of transistor 302 is connected to the inverting input of the operational amplifier 300; see [0090] of Fort, “having its other conduction terminal connected to the second input of amplifier 300, that is, the inverting input”); and adjusting the gate voltage in a direction that reduces a difference between the voltage at the source of the transistor and the reference voltage (the non-inverting input of the operational amplifier 300 receives the potential VREF and the output of the operational amplifier 300 delivers the signal cmd2 to the gate of transistor 302 so that the source potential of transistor 302 is equal to the potential VREF; see [0091] of Fort, “the gate of transistor 302 is connected to the output of amplifier 300”, and see [0100] of Fort, “the source potential of transistor 302 is equal to potential VREF via amplifier 300, the source potential Vout of transistor 110 is thus also equal to potential VREF”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for operating a voltage regulator of Wang to comprise sensing a voltage at a source of the transistor and adjusting the gate voltage in a direction that reduces a difference between the voltage at the source of the transistor and the reference voltage, as taught by Fort, because it can help the voltage at the source of the transistor be equal to the reference voltage in steady state and thereby better control the gain between the reference voltage and the regulated output voltage (see [0103] of Fort, “the circuit 124 of FIG. 4 enables, in steady state, to better control the gain between potential VREF and potential Vout”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2019/0171243 A1 discloses a flip voltage follower low dropout regulator in which an operational amplifier drives the gates of a source follower device and of a replica source follower device, a bias device is coupled between the drain of each source follower device and a power supply rail, and the gate of a gain device is coupled to the drain of the corresponding source follower device.
US 2005/0134383 A1 discloses a class AB source follower in which an over-limit current condition at the drain of an NMOS source follower is sensed by a common source device of the opposite conductivity type that supplies additional current to the output load, thereby permitting a drive current greater than the quiescent current.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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