Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-20 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12254951. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-7 and 10 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a memory device comprising: a memory array including memory cells; and a page buffer coupled to the memory cells, and the page buffer including:
The claim 1 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites : a first transistor, wherein the first transistor is coupled to a bit line input of the page buffer while in the reference claimed silence. However, Fig. 6 of Cho US Pub. No. 20230060080 disclose the first transistor TR1, wherein the first transistor is coupled to a bit line input of the page buffer; or the first transistor NM5 of Fig. 6 of Cho et al. US Pub. No. 20220020404.
The claims 8 and 9 of examined application are obvious over the claim1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a fifth PMOS transistor while in the reference claimed silence. However, the fifth PMOS transistor PM’ of Fig. 6 of Cho et al. US Pub. No. 20220020404.
Claim 10 is also obvious by a paragraph 81 and Fig. 6A of Chen et al. US Pub. No. 20220415370 for a C latch and a LVT latch or the L1 and L2 in Fig. 3 of Ogawa US Pub. No. 20160267988.
Claims 11-17 of the examined application are anticipated and the same scope of invention by claims 11-16 of the reference such as a memory system comprising: a memory device including: a memory array including memory cells; and a page buffer coupled to the memory cells, and the page buffer including:
The claim 11 of examined application are obvious over the claim 11 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites : a first transistor, wherein the first transistor is coupled to a bit line input of the page buffer while in the reference claimed silence. However, Fig. 6 of Cho US Pub. No. 20230060080 disclose the first transistor TR1, wherein the first transistor is coupled to a bit line input of the page buffer; or the first transistor NM5 of Fig. 6 of Cho et al. US Pub. No. 20220020404.
Claim 18 of the examined application is method claims but they encompass the same scope of invention as to that of apparatus claim 1 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method for operating a memory device, wherein the memory device includes a page buffer and a plurality of memory cells, the page buffer includes:
The claim 18 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites : a first transistor, wherein the first transistor is coupled to a bit line input of the page buffer while in the reference claimed silence. However, Fig. 6 of Cho US Pub. No. 20230060080 disclose the first transistor TR1, wherein the first transistor is coupled to a bit line input of the page buffer; or the first transistor NM5 of Fig. 6 of Cho et al. US Pub. No. 20220020404.
Claims 19 and 20 are obvious to the claim 7 or 18 and Fig. 6C of Shi et al. US Pub. No. 20240062831.
5. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827
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