DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Enomoto (JP H0746098 A).
Regarding claim 1, Enomoto teaches an apparatus, comprising:
a logic circuit configured to receive a target signal (Fig. 1, inverter, 1-3 and 1-4); and
a capacitive device (Fig. 1, 1-8, a capacitor) including one terminal coupled to a first node on an output side of the logic circuit (1-12) and another terminal coupled to a second node on an input side of the logic circuit (1-11).
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (CN 202110765926 A).
Regarding claim 21, Hu teaches an apparatus, comprising:
a memory device (page 2, Technical Field, memory); and
a slew rate control circuit (Fig. 2) configured to control a slew rate of a signal for the memory device, the slew rate control circuit including:
a logic circuit configured to receive the signal (Fig. 2, inverter, P12 and N13); and
a capacitive device (C11) including one terminal coupled to a first node on an output side of the logic circuit to provide first capacitance at the first node (v4), and further including another terminal coupled to a second node on an input side of the logic circuit to provide second capacitance at the second node (v3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-12 are rejected under 35 U.S.C. 103 as being unpatentable over Enomoto (JP H0746098 A) in view of Van der Tempel (US 2017/0214878 A1).
Regarding claim 2, all the limitations of claim 1 are taught by Enomoto.
Enomoto does not explicitly teach the apparatus, wherein the capacitive device comprises a transistor, a gate of the transistor is coupled to one of the first node and the second node, and at least a body of the transistor is coupled to another of the first node and the second node.
Van der Tempel teaches an apparatus, wherein a capacitive device comprises a transistor, a gate of the transistor is coupled to one of a first node and a second node (Fig. 4,
C
H
D
R
), and
at least a body of the transistor is coupled to another of the first node and the second node (Fig. 4,
C
H
D
R
, body to ground).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Enomoto with a MOS transistor as taught by Van der Tempel, since such implementation is well-known and conventional in the art (Van der Tempel, [0048]).
Regarding claim 3, all the limitations of claim 2 are taught by Enomoto in view of Van der Tempel.
Enomoto in view of Van der Tempel further teaches the apparatus wherein a source and a drain of the transistor are coupled to the other of the first node and the second node (Enomoto, Fig. 1, 1-8, a capacitor, one node is coupled to input and the other node is coupled to the output of the inverter).
Regarding claim 4, all the limitations of claim 2 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein the body of the transistor is supplied with a fixed voltage (Fig. 4,
C
H
D
R
, body to ground).
Regarding claim 5, all the limitations of claim 4 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein the transistor of the capacitor device is a first transistor (Fig. 4,
C
H
D
R
).
Enomoto further teaches the apparatus wherein the logic circuit comprises an inverter including a second transistor, and a body of the second transistor of the inverter is supplied with the fixed voltage (Fig. 1, 1-3, PMOS whose body is tied to VDD).
Regarding claim 6, all the limitations of claim 2 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein the transistor of the capacitor device is a first transistor (Fig. 4,
C
H
D
R
).
Enomoto further teaches the apparatus wherein the logic circuit comprises an inverter including a second transistor, and
Enomoto in view of Van der Tempel teaches the apparatus wherein the body of the first transistor of the capacitive device is electrically independent of a body of the second transistor of the inverter (Fig. 1, 1-3, PMOS whose body is tied to VDD).
Regarding claim 7, all the limitations of claim 1 are taught by Enomoto.
Enomoto does not explicitly teach the apparatus, wherein
the capacitive device comprises a transistor,
a gate of the transistor is coupled to one of the first node and the second node, and
a source and a drain of the transistor is coupled to another of the first node and the second node.
Van der Tempel teaches an apparatus, wherein a capacitive device comprises a transistor (Fig. 4,
C
H
D
R
), a gate of the transistor is coupled to one of a first node and a second node (
V
G
A
T
E
), and a source and a drain of the transistor is coupled to another of the first node and the second node (FD).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Enomoto with a MOS transistor as taught by Van der Tempel, since such implementation is well-known and conventional in the art (Van der Tempel, [0048]).
Regarding claim 8, all the limitations of claim 7 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein a body of the transistor is coupled to the other of the first node and the second node (Fig. 4,
C
H
D
R
, body coupled to ground).
Regarding claim 9, all the limitations of claim 7 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein a body of the transistor is supplied with a fixed voltage. (Fig. 4,
C
H
D
R
, body coupled to ground).
Regarding claim 10, all the limitations of claim 9 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein the transistor of the capacitor device is a first transistor (Fig. 4,
C
H
D
R
).
Enomoto further teaches the apparatus wherein the logic circuit comprises an inverter including a second transistor, and a body of the second transistor of the inverter is supplied with the fixed voltage (Fig. 1, 1-3, PMOS whose body is tied to VDD).
Regarding claim 11, all the limitations of claim 7 are taught by Enomoto in view of Van der Tempel.
Van der Tempel further teaches the apparatus wherein the transistor of the capacitor device is a first transistor (Fig. 4,
C
H
D
R
).
Enomoto further teaches the apparatus wherein the logic circuit comprises an inverter including a second transistor, and
Enomoto in view of Van der Tempel teaches the apparatus wherein the body of the first transistor of the capacitive device is electrically independent of a body of the second transistor of the inverter (Fig. 1, 1-3, PMOS whose body is tied to VDD).
Regarding claim 12, all the limitations of claim 1 are taught by Enomoto.
Enomoto does not explicitly teach the apparatus, wherein the capacitive device is a first capacitive device including a first transistor,
the apparatus further comprises a second capacitive device including a second transistor,
gates of the first and second transistors are coupled to one of the first node and the second node, and sources, drains, and bodies of the first and second transistors are coupled to another of the first node and the second node.
Van der Tempel teaches the apparatus wherein the transistor of the capacitor device is a first transistor (Fig. 4,
C
H
D
R
),
gate of the first transistor is coupled to one of a first node and a second node, and sources, drains, and bodies of the first transistor is coupled to another of the first node and the second node (Fig. 4,
C
H
D
R
, coupled to
V
G
A
T
E
and FD).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Enomoto with a MOS transistor as taught by Van der Tempel, since such implementation is well-known and conventional in the art (Van der Tempel, [0048]).
The combined teachings of Enomoto and Van der Tempel do not explicitly teach the apparatus further comprising a second capacitive device including a second transistor.
However, it would have been obvious to one of ordinary skill in the art at the time of invention was made to use multiple capacitive devices with the invention of Van der Tempel because it would be merely duplication of parts. The court has held the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see MPEP 2144.04).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Enomoto (JP H0746098 A) in view of Van der Tempel (US 2017/0214878 A1) as applied to claim 12 above, and further in view of Lu (US 10164640 B1).
Regarding claim 13, all the limitations of claim 12 are taught by Enomoto in view of Van der Tempel.
Enomoto in view of Van der Tempel does not explicitly teach the apparatus, wherein the source, the drain, and the body of each of the first and second transistors are coupled to each other at a third node, and the third node is coupled to the other of the first node and the second node.
Lu teaches an apparatus, wherein the source, the drain, and the body of a transistor are coupled to each other at a third node (Fig. 3, 310).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Enomoto in view of Van der Temple as taught by Lu since the MOS capacitor 310 is another well-known and conventional MOS transistor implementation of a capacitor in the art.
Claims 18-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (CN 202110765926 A) in view of Lu (US 10164640 B1).
Regarding claim 18, Hu teaches an apparatus comprising:
an inverter configured to receive a target signal for slew rate control (Fig. 2, P12 and N13); and
a capacitive device comprising a first node coupled to one of an input side and an output side of the inverter (v3) and a second node coupled to another of the input side and the output side of the inverter (v4).
Hu does not explicitly teach the apparatus wherein the capacitive device comprises a MOS transistor, the MOS transistor including a gate coupled to a first node and wherein the source, the drain and the body of the MOS transistor are coupled to each other at a third node.
Lu teaches an apparatus, wherein the capacitive device comprises a MOS transistor, the MOS transistor including a gate coupled to a first node and wherein the source, the drain and the body of the MOS transistor are coupled to each other at a third node (Fig. 3, 310).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Hu as taught by Lu since the MOS capacitor 310 is well-known and conventional in the art.
Regarding claim 19, all the limitations of claim 18 are taught by Hu in view of Lu.
Lu further teaches the apparatus wherein the MOS transistor is an n-channel type MOS transistor or a p-channel type MOS transistor (Fig. 3, 310).
Regarding claim 20, all the limitations of claim 18 are taught by Hu in view of Lu.
Lu further teaches the apparatus wherein the MOS transistor is a first MOS transistor, and the gate, the source, the drain and the body thereof are a first gate, a first source, and a first drain, and a second body (Fig. 3, 310).
Lu does not explicitly teach the apparatus wherein the capacitive device further comprises a second MOS transistor, the second MOS transistor including a second gate coupled to the first node, and further including a second source, a second drain, and a second body coupled to the second node.
However, it would have been obvious to one of ordinary skill in the art at the time of invention was made to use multiple capacitive devices with the invention of Lu because it would be merely duplication of parts. The court has held the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see MPEP 2144.04).
Regarding claim 22, all the limitations of claim 21 are taught by Hu.
Hu does not explicitly teach the apparatus wherein the capacitive device comprises a MOS transistor, the first node is coupled to one of a gate of the MOS transistor and a source-drain-body node of the MOS transistor, and the second node is coupled to another of the gate of the MOS transistor and the source- drain-body node of the MOS transistor.
Lu teaches an apparatus, wherein the capacitive device comprises a MOS transistor, including a gate of the MOS transistor and a source-drain-body node of the MOS transistor (Fig. 3, 310).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to implement the capacitor of Hu as taught by Lu since the MOS capacitor 310 is well-known and conventional in the art.
Allowable Subject Matter
Claims 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, the prior arts fail to teach or reasonably suggest an apparatus, comprises a switch circuit configured to connect and disconnect the capacitive device to and from at least one of the first node and the second node, in combination with the other limitations of the claim.
Claims 15-17 are objected to due to their dependencies to claim 14 above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Korner (DE 102016110383 B4) teaches an apparatus comprises an inverter configured to connect the capacitive device to and from at least one of the first node and the second node (Fig. 2, 200, 211).
Conclusion
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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