DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 29th, 2026, has been entered.
Response to Amendment
Applicant’s Remarks/Arguments filed on April 29th, 2026, have been carefully considered.
Claims 1 and 30 have been amended.
Claims 8-9, 11-13, 15, 19-21, 23, and 28-29 has been canceled.
No claims have been added.
Clams 1-7, 10, 14, 16-18, 22, 24-27, and 30-31 are currently pending in the instant application
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Priority
Applicant appears to argue that 3/7/2012 is the earliest priority date for the present application. The examiner requests applicant provide where support can be found for the latest amendments to claims 1 and 30 that shows detailed support for priority to 3/7/2012.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 10, 14, 16-18, 24-27, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach [US2012/0196409] hereinafter Bach, in view of Chen et al. [US2010/0320565] further in view of Dahlberg et al. [US2005/0105349]. Or-Bach teaches 3D semiconductor device. Chen teaches wafer and method for improving yield rate of wafer. Dahlberg teaches programming data strobe offset with DLL for double data rate (DDR) ram memory.
Regarding claims 1 and 30, Bach teaches an apparatus [Bach abstract “…a semiconductor device…”], comprising:
a first semiconductor platform including a first memory [Bach paragraph 0015, first lines “…first transistor layer… a plurality of sequential cells”]; and
a second semiconductor platform stacked with the first semiconductor platform [Bach paragraph 0015, middle lines “…a second transistor layer overlaying the first transistor layer…”], the second semiconductor platform including a second memory [Bach paragraph 0015, last lines “…transistors of second transistor layer…”];
circuitry in communication with the first semiconductor platform and the second semiconductor platform [Bach paragraph 0114, first lines “…A possible fabrication method for constructing the programming circuitry in an Attic above the functional circuitry on the base silicon is by bonding a programming circuitry wafer on top of functional circuitry wafer using Through Silicon Vias…”], the circuitry:
identifying one or more faulty components of the apparatus [Bach paragraph 0201, last lines “…the defect can develop into a failure which may be detected during subsequent tests in the field…”], the identified one or more faulty components capable of including:
Bach fails to explicitly teach a bus that utilizes a first through-silicon via (TSV) in communication between the first semiconductor platform and the second semiconductor platform.
However, Chen does teach a bus that utilizes a first through-silicon via (TSV) in communication [Chen paragraph 0009, first lines “…a function of the TSV is generally categorized into four types: signal transmission, power delivery, thermal conduction, and input/output port connection…”] between the first semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of upper…layers via the TSVs…”] and the second semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of…lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”].
Bach and Chen are analogous arts in that they both deal with repairing failed TSV.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bach’s semiconductor platform with Chen’s detailed teachings of repairing failed TSV with spare TSV for the benefit of providing spare TSV during production to increase both yield and reliability [Chen paragraph 0010, middle lines “…the yield is increased and the reliability is enhanced, but an area of the wafer is increased as well…”].
a memory cell of at least one of the first memory or the second memory [Bach paragraph 0195, middle lines “…Examples of such include, but are not limited to, analog blocks, I/O, memory, and other blocks…” and paragraph 0249, middle lines “…When a bad block is detected, an entire new block would need to be crafted on the Repair Layer with Direct-Write e-Beam…” and paragraph 0178, all lines “…The idea is to tile the whole wafer with a dense pattern of memory cell, and then customize it using selective etching as before, and providing the required non-repetitive structures through an adjacent logic layer below or above the memory layer. FIG. 23A is a drawing illustration of a typical 6-transistor SRAM cell 2320, with its word line 2322, bit line 2324 and its inverse 2326. Such bit cell is typically densely packed and highly optimized for a given process…A four by four array 2332 may be defined through custom etching away the cells in channel 2334, leaving bit lines 2336 and word lines 2338 unconnected. These word lines 2338 may be then connected to an adjacent logic layer below that will have a word decoder 2350 in FIG. 23C that will drive them through outputs 2352. Similarly the bit lines may be driven by another decoder such as 2360 in FIG. 23D through its outputs 2362. A sense amplifier 2368 is also shown. A critical feature of this approach is that the customized logic can be provided from below or above in close vertical proximity to the area where it is needed assuring high performance customized memory blocks…"]; and
adjusting at least one aspect of the apparatus to repair the identified one or more faulty components including: the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0009, first lines “…a function of the TSV is generally categorized into four types: signal transmission, power delivery, thermal conduction, and input/output port connection…” and paragraph 0026, last lines “…inside wafers of upper and lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”], in response to the identification of the one or more faulty components of the apparatus that includes the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…after the wafer 600 has been manufactured and tested to find the failure of the TSV 605, a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604…”].
wherein the apparatus is configured such that the adjusting:
causes a change with respect to at least one of a first plurality of circuits in communication with the first TSV that is in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive…”(Where a first plurality of circuits is extremely broad and allows an anti-fuse to read on the claim language.)], and
causes a change with respect to at least one of a second plurality of circuits in communication with the first TSV that is in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…and the switching unit 609 is programmed to be conductive…”(Where a second plurality of circuits is extremely broad and allows switches to read on the claim language.)],
such that the identified one or more faulty components including the bus that utilizes the first TSV is repaired [Chen paragraph 0031, last lines “…The spare TSV 604 passes through the wafer 600 vertically, and is used to replace the failed TSV 603 or 605 when the TSV 603 or 605 has failed…”], by the bus utilizing a second TSV [Chen paragraph 0031, last lines “…The spare TSV 604…”] in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of the upper layer and lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”], instead of the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0031, middle lines “…The TSV 603 passes through the wafer 600 vertically and is coupled to the circuit unit 601 via the front metal of the wafer 600. The TSV 605 passes through the wafer 600 vertically and is coupled to the circuit unit 602 via a front metal of the wafer 600. Hence, the circuit units 601 and 602 are capable of transmitting signals with circuit units (not shown) inside wafers of upper and lower layers via the TSVs 603 and 605 respectively…”], as a result of the change with respect to the at least one of the first plurality of circuits and the change with respect to the at least one of the second plurality of circuits [Chen paragraph 0035, all lines “…a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604…”].
Bach and Chen fail to explicitly teach wherein the apparatus is configured such that the circuitry includes a timing control circuit that, during an initialization of the apparatus, measures to determine one or more delay properties of one or more interconnect structures, for adjusting a signal timing to align with one or more strobes.
However, Dahlberg does teach the apparatus is configured such that the circuitry includes a timing control circuit that [Dahlberg paragraph 0016, middle lines “…employing a delay locked loop (DLL) circuit to delay the data access signal to the center of a data window…”], during an initialization of the apparatus [Dahlberg paragraph 0017, most lines “…a DQS strobe controller for a double data rate (DDR) memory device comprises a delay line formed by a plurality of programmable delay elements to provide an initial delay. An adder/subtracter element implements a fine tuning adjustment of the initial delay. The fine tuning adjustment is determined empirically by operation of the DQS strobe controller in operation with the DDR memory device…”], measures to determine one or more delay properties of one or more interconnect structures [Dahlberg paragraph 0025, middle lines “…the initial delay determined by the DLL is importantly also fine tuned with an offset empirically determined, e.g., by a memory test…” and paragraph 0005, first lines “…the DDR SDRAM…”], for adjusting a signal timing to align with one or more strobes [Dahlberg paragraph 0010, last lines “…To capture the data from the DDR, the controller must delay the received DQS strobes so that the strobe transition occurs as close as possible to the center of the received data window, or "eye"…”].
Bach, Chen, and Dahlberg are analogous arts in that they all deal with improving computer memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of both Bach and Chen with Dahlberg’s initial delay measurements for the benefit of obtaining the optimal DQS centering values for peak performance [Dahlberg paragraph 0015, most lines “…for centering DQS data strobes based on actual, optimal values…”].
Regarding claim 2, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a logic chip [Bach paragraph 0118, first lines “…Logic Blocks are constructed to implement programmable logic functions…”].
Regarding claim 3, as per claim 1, Bach teaches the apparatus is configured such that the circuitry is located on a same die as at least one of the first semiconductor platform or the second semiconductor platform [Bach paragraph 0134, last lines “…which the Through Silicon Via is continuing vertically through all the dies constructing a global cross-die connection. FIG. 9B provides an illustration of similar sized dies constructing a 3D system. 9B shows that the Through Silicon Via 404 is at the same relative location in all the dies constructing a standard interface…”].
Regarding claim 4, as per claim 1, Bach teaches the apparatus is configured such that the circuitry is located on a same die as a processor that is separate from the first semiconductor platform and the second semiconductor platform [Bach figure 24A, feature 2434 “BIST Controller” is external to the layers 2412 and 2402].
Regarding claim 5, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer in communication with an input/output pin [Bach paragraph 0017, first lines “…The selectively coupleable additional input can be a multiplexer. A programmable element can be provided to control said multiplexer…” and paragraph 0247, last lines “…Then the BIST controllers of each block can coordinate locally and decide which block should have its inputs and outputs coupled to Layer 1 through the Layer 1 multiplexers 3722 and 3724…”].
Regarding claim 6, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer, and the circuitry is programmable [Bach paragraph 0193, first lines “…It should be noted that if multiplexer controls 2641 and 2642 are reprogrammable as in using memory cells…”] at manufacture before run time [Bach paragraph 0201, first lines “…The exemplary embodiments discussed so far are primarily concerned with yield enhancement and repair in the factory prior to shipping a 3D IC to a customer…”]., in response to the identification of the one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”].
Regarding claim 7, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer, and the circuitry is programmable [Bach paragraph 0193, first lines “…It should be noted that if multiplexer controls 2641 and 2642 are reprogrammable as in using memory cells…”] at run time [Bach paragraph 0189, last lines “…Similar repair approach can also assist systems that require self-healing ability at every power-up sequence through use of memory-based repair structures as described…”], in response to the identification of the one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”].
Regarding claim 10, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in a non-permanent repair, utilizing a look-up table, of the identified one or more faulty components of the apparatus that includes one or more memory locations, such that the look-up table is utilized to substitute the one or more memory locations with one or more other memory locations [Bach paragraph 0121, first lines “…FIG. 6 is a drawing illustration of one possible implementation of a four input lookup table 600 ("LUT4") that can implement any combinatorial function of 4 inputs…”].
Regarding claim 14, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components, utilizing one or more fuses [Bach paragraph 0302, middle lines “…A programmable technology like, for example, fuses, antifuses, flash memory storage, etc., could be used to effect both factory repair and field repair…”(The examiner has determined that using a fuse is permanent repair.)].
Regarding claim 16, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”], utilizing repair information on one or more repair actions that is communicated between a separate processor and the circuity [Bach paragraph 0182, middle lines “…During manufacturing, after the IC has been finalized to metal 5 of the repair layer, the chips on the wafer are powered up through a tester probe, the BIST is executed, and faulty FFs are identified. This information is transmitted by BCC to the external tester, and is driving the repair cycle…”].
Regarding claim 17, as per claim 1, Bach teaches the apparatus is configured such that the circuitry performs a self-test [Bach paragraph 0227, first lines “…Using some form of Built In Self Test (BIST) has the advantage of being self contained inside 3D IC…”] utilizing one or more patterns applied to one or more portions of at least one of the first semiconductor platform or the second semiconductor platform [Bach paragraph 0226, middle lines “…then automatic test pattern generated (ATPG) vectors may be used in a manner similar to the factory repair embodiments…”].
Regarding claim 18, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a built- in self-test (BIST) controlled utilizing signals that are independent of memory signals [Bach paragraph 0227, first lines “…Using some form of Built In Self Test (BIST) has the advantage of being self contained inside 3D IC…” and paragraph 0236, first lines “…n order to repair a 3D IC like 3D IC 3300 of FIG. 33A using the block BIST approach, the part is put in a test mode and the DATA1 and DATA2 signals are compared at each scan flip-flop 3200 on Layer 1 and Layer 2 and the resulting ERROR1 and ERROR2 signals are monitored as described in the embodiments above or possibly using some other method…”(The examiner has determined DATA and ERROR to be different signals and thus BIST ERROR signals are independent from memory DATA signals].
Regarding claim 24, as per claim 1, Bach teaches the apparatus is configured such that the at least portion of a memory array includes a subarray of the memory array [Bach paragraph 0013, last lines “…semiconductor layer comprise repeating memory structure with sub structures defined by etching…” and paragraph 0173, all lines “…a section of a Gate Array terrain with a repeating transistor cell structure. The cell is similar to the one of FIG. 20C wherein the respective gate of the N transistors are connected to the gate of the P transistors. FIG. 20D illustrate an implementation of basic logic cells: Inv, NAND, NOR, MUX..”].
Regarding claim 25, as per claim 1, Bach teaches the apparatus is configured such that the subarray corresponds to a portion of the memory array corresponding to a row buffer [Bach paragraph 0010, middle lines “…the part also has a variety of input/output cells 2920, each comprising a bond pad 2922, an input buffer 2924, and a tri-state output buffer 2926…”].
Regarding claim 26, as per claim 1, Bach teaches the apparatus is configured such that access to the first memory is divided into one or more virtual channels addressed utilizing an address field [Bach paragraph 0267, first lines “…The row and column addresses are virtual addresses, since in a logic design the locations of the flip-flops will not be neatly arranged in rows and columns…”].
Regarding claim 27, as per claim 1, Bach teaches the apparatus is configured such that the circuit periodically performs error detection and error scrubbing during runtime [Bach paragraph 0214, last lines “…Cyclic Redundancy Checking may be employed. These methods all involve stopping system operation and entering a test mode. Other methods of monitoring possible error conditions in real time will be discussed below…” and paragraph 0280, middle lines “…The ability to fix defects in the factory with Repair Layers combined with the ability to automatically fix delayed defects (by masking them with three layer TMR embodiments or replacing faulty circuits with two layer replacement embodiments) allows the creation of much larger and more complex three dimensional systems…”].
Regarding claim 31, as per claim 1, Chen teaches wherein the apparatus is configured such that changes are caused with respect to multiple of the first plurality of circuits and multiple of the second plurality of circuits, in response to the identification of the one or more faulty components of the apparatus that includes the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035-0036, all lines “…after the wafer 600 has been manufactured and tested to find the failure of the TSV 605, a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604. However, after the wafer 600 has been manufactured and tested to find the failure of the TSV 603, then a voltage is respectively applied to the two metal layers of the anti-fuse 606 in the present exemplary embodiment, so that the anti-fuse 606 is changed from the original on-state to the short circuit state and the switching unit 608 is programmed to be conductive. Therefore, the spare TSV 604 replaces the failed TSV 603, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the spare TSV 604 and the TSV 605…”].
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach [US2012/0196409] hereinafter Bach, in view of Chen et al. [US2010/0320565] in view of Dahlberg et al. [US2005/0105349] further in view of Shirota et al. [US2009/0040856]. Or-Bach teaches 3D semiconductor device. Chen teaches wafer and method for improving yield rate of wafer. Dahlberg teaches programming data strobe offset with DLL for double data rate (DDR) ram memory. Shirota teaches semiconductor memory device changing refresh interval depending on temperature.
Regarding claim 22, as per the combination in claim 21, Bach, Chen, and Dahlberg fail to explicitly teach the apparatus is configured such that temperature-based refresh timing-related information is encoded for being conveyed to control a refresh of the first memory that includes dynamic random access memory (DRAM), where the temperature-based refresh timing-related information is updated utilizing stored information, in response to a temperature change.
However, Shirota does teach the apparatus is configured such that temperature-based refresh timing-related information is encoded for being conveyed to control a refresh of the first memory that includes dynamic random access memory (DRAM), where the temperature-based refresh timing-related information is updated utilizing stored information, in response to a temperature change [Shirota abstract “…a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit…” and paragraph 0053, last lines “…When changes in the detected-temperature signals Ext_state1 through Ext_staten indicate a temperature rise…” and paragraph 0006, middle lines “…DRAMs, on the other hand, perform refresh operations at constant intervals to retain data, and consume power to some extent even in the standby state…” and paragraph 0051, last lines “…The counter circuit 19 receives a refresh request signal generated by the frequency dividing circuit 15, and counts the number of refresh request signals. When the temperature detector 18 detects a transition from a high temperature state to a low temperature state, the counter circuit 19 starts counting. The refresh intervals are changed after the count reaches a predetermined value…”].
Bach, Chen, Dahlberg and Shirota are analogous arts in that they both deal with improving memory reliability.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bach’s, Chen’s, and Dahlberg’s combined teachings of repairable memory layers with Shirota’s temperature dependent refresh cycles for the benefit of improving data retention in changing refresh rates which avoid situations that can lead to destruction of data [Shirota paragraph 0049, last lines “…Provision is thus made to avoid an undesirable event in which switching the refresh intervals to longer intervals causes destruction of data despite a need for shorter-interval refresh operations for the memory cells having been placed in the high temperature state…”].
Response to Arguments
Applicant’s arguments with respect to claims 1 and 30 have been considered but are moot in view of new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Thorne [US7,222,036] Thorne also teaches a startup measurement of memory delay for startup calibration as seen in column 4, lines 1-15.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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