DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on July 18th, 2025, have been carefully considered.
Claims 1, 6, 7, 11, 18 and 30 have been amended.
Claim 29 has been canceled.
Claim 31 has been added.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Priority
Applicant has established in the response dated July 18th, 2025, that the earliest possible date for priority concerns is application 13/710,411 filed on 12/10/2012 and issued as patent # 9,432,298. Therefore, 12/10/2012 is considered the priority date henceforth. However, Examiner does not concede that application 13/710,411 provides adequate teachings for all priority concerns. Any claim that cannot establish priority will be given the current applications filing date of 1/23/2025.
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C.119(e) or 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 13/441,132 or 13/710,411, or 14/589,937 fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
Accordingly, claims 1-30 are not entitled to the benefit of the prior applications
Regarding claim 8, the examiner fails to find the priority documents that teach “the adjusting results in the repair of the identified one or more faulty components of the apparatus, which includes at least a portion of a bank of the first memory that corresponds to a row address”, the applicant provides a citation that merely mentions row address and memory bank. However, the citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 9, the examiner fails to find the priority documents that teach “the adjusting results in a permanent repair of identified the one or more faulty components of the apparatus”. Examiner fails to see from the provided citations how “permanent repairs” can be adjusted if they are permanent and thus fails to provide priority for the limitation as a whole.
Regarding claim 11, the examiner fails to find priority from applicant’s citations that the “first TSV of the bus” where the first TSV is “of the bus”. Examiner requests applicant provide a better citation.
Regarding claim 12, the examiner fails to find the priority documents that teach “the apparatus is configured such that the identified one or more faulty components includes at least one lane”. Applicant’s citation provides mentioning of lane configuration but does not teach the claim limitation as a whole where the faulty component includes lanes. The citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 13, the examiner fails to find the priority documents that teach “the apparatus is configured such that the adjusting includes reallocating one or more wire connections”. Applicant’s citation provides mentioning wire allocations but does not teach the claim limitation as a whole where the adjusting includes reallocating one or more wire connections. The citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 15, the examiner fails to find the priority documents that teach “the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components of the apparatus, utilizing one or more spare memory resources in a stacked memory package including the first semiconductor platform and the second semiconductor platform, where a number of the one or more spare memory resources is communicated via a control bus”. Applicant’s citations merely mention the word control and spare circuits but does not teach the claim limitation as a whole where the adjusting results in the repair…utilizing one or more space memory resources…where the number of spare memory resources are communicated via a control bus. The citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 19, the examiner fails to find the priority documents that adequately teach “the apparatus is configured such that the adjusting is in connection with a write or read command, and the at least one aspect includes a configuration of a register that is adjusted in response to the write or read command”. Applicant’s citation fails to provide a teaching as a whole where the adjusting is in response to the write or read command.
Regarding claim 20, as per claim 1, the examiner fails to find the priority documents that adequately teach “the apparatus is configured such that the identifying is performed by the circuitry, utilizing a loopback function and a linear feedback shift register (LFSR)”. Applicant’s citation teaches a loopback function but fails to provide a teaching of a linear feedback shift register where the claim as a whole requires them both since the limitation is an AND limitation and thus there needs to be a teaching of the whole limitation including both the loopback function and feedback shift register together.
Regarding claim 23, as per claim 1, the examiner finds teachings of grouping in various priority documents but fails to find a teaching in the priority documents of “a plurality of TSV data buses that are divided into one or more groups each corresponding to at least a portion of a memory array of at least one of the first semiconductor platform or the second semiconductor platform”. Applicant’s citations fail to provide an adequate teaching of TSV data buses divided into one or more groups where each group has a portion of the memory array. The examiner fails to find that teaching as a whole.
The examiner requests the applicant provide the location in each support document that verifies the support document adequately satisfies the written description requirement for each of the identified claim limitations being taught as a whole. If adequate support cannot be found then the claim limitations will receive the filing date of the present application which is January 23rd, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 12, 13, 20, 21, and 23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 12, the claim is drawn to “one or more faulty components includes at least one lane”. The examiner finds multiple teachings of a lane in the specification however, the examiner fails to find specific support in the specification for a one of the faulty components being a lane. Applicant’s citation provides mentioning of lane configuration but does not teach the claim limitation as a whole where the faulty component includes lanes. The citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 13, the claim is drawn to “the adjusting includes reallocating one or more wire connections”. The examiner fails to find specific support in the specification for a reallocating one or more wires to accomplish the repair function. Applicant’s citation provides mentioning wire allocations but does not teach the claim limitation as a whole where the adjusting includes reallocating one or more wire connections. The citation fails to provide a full teaching of the claim limitation as a whole, where the citation only provides a dictionary of different elements that could not be considered to definitely teach the claim as a whole.
Regarding claim 20, the claim is drawn to “the identifying is performed by the circuitry, utilizing a loopback function and a linear feedback shift register (LFSR)”. The examiner fails to find adequate support for the claim limitation as a whole in the present specification. The examiner finds support for registers but does not find support for utilizing a loopback function AND a linear feedback shift register (LFSR). Applicant’s citation teaches a loopback function but fails to provide a teaching of a linear feedback shift register where the claim as a whole requires them both since the limitation is an AND limitation and thus there needs to be a teaching of the whole limitation including both the loopback function and feedback shift register together.
Regarding claim 21, the claim is drawn to “temperature-based refresh timing-related information is encoded for being conveyed to control a refresh of the first memory that includes dynamic random access memory (DRAM)”. The examiner fails to find adequate support for the claim limitation as a whole in the present specification. The examiner finds a mention of temperature throttling but does not teach the temperature is used to control refresh timing or that such refresh timing is encoded for use by DRAM.
Regarding claim 23, the claim is drawn to “a plurality of TSV data buses that are divided into one or more groups each corresponding to at least a portion of a memory array of at least one of the first semiconductor platform or the second semiconductor platform”. The examiner fails to find adequate support for the claim limitation as a whole in the present specification. The examiner finds teachings of groups but fails to find support for a plurality of TSV data buses being divided into groups corresponding to a portion of an array from either the first or second semiconductor platform. Applicant’s citations fail to provide an adequate teaching of TSV data buses divided into one or more groups where each group has a portion of the memory array. The examiner fails to find that teaching as a whole.
Furthermore, the examiner has determined that one of ordinary skill would not know to scour through multiple incorporated specifications to piece together the current invention. One of ordinary skill would not understand how one section of one specification relates to another section in another specification. The examiner further determines that the specifications fail to teach the claims as a whole, with the level of specificity required to show one of ordinary skill in the art how to recreate the invention.
The examiner fails to find any support in the applicant’s immediate specification or any of those incorporated by reference that teaches the claim limitation with any level of specificity that proves the applicant owned the claimed invention at the time of filing.
As explained above, rejections have been issued under 35 U.S.C. §112, first paragraph, as failing to comply with the written description requirement. The rejected claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. In advancing this rejection, the Examiner has followed MPEP §2163.04(I)(B), which has been approved by the United States Court of Appeals for the Federal Circuit. See Hyatt v. Dudas, 492 F.3d 1365, 1370 (Fed. Cir. 2007) (holding that MPEP §2163.04(I)(B) is a lawful formulation of the prima facie standard for lack of written description rejection).
Furthermore, applicant’s specification does not disclose the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. E.g. Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015) and MPEP § 2161.01(I).
Consistent with the USPTO Written Description Guidelines, there are two primary written description issues that applicant must resolve. See generally MPEP 2163 (incorporating the USPTO Written Description Guidelines). First, the claims recite combinations of the particular individual elements interconnected and interrelated to perform one or more functions. The specification does not contain a coherent embodiment that describes the entire combination of claimed elements along with the interconnections and interrelations between them. The specification does not have a coherent description of the set of operations corresponding to the claim limitations. Claims reciting elements “in response to” other elements require the specification to describe these interconnections as claimed. Therefore, in order for the specification to provide written description of the claims, the specification needs to describe both the individual claim elements and limitations and the interconnection between the elements and limitations that form the claimed embodiment. While the failure of the specification to disclose a specific element may be fatal to patentability, a showing of descriptive support for that element or limitation alone does not solve the problem fundamental to applicant’s claims: a failure to adequately describe the interconnections between the various individual elements and limitations working cooperatively and a failure to describe the claims as a whole.
A simple analogy would be giving a person a bunch of separate cooking ingredients such as flour, sugar, butter, and milk and asking them to bake a cake but not give them the recipe for the cake. Better yet, just supplying those ingredients does not describe all possible combinations of baked goods that can be created. The examiner has found there to be no step-by-step recipe as is required under 112(a). There are no teachings of when A happens then B happens and this leads to either C or D. The specification is void of all instructions related to the current claim language.
The examiner has been unable to find adequate demonstration in the specification that applicant possessed the particular claimed combination of individual elements. Thus, even if some elements may be individually described, the specification fails to support the claimed embodiment as a whole. See 37 C.F.R. 1.71(b). Put differently, applicant must show possession of the claimed invention as a whole, as opposed to a hypothetical sum of parts scattered across the specification.
Second, for some claims, the specification fails to adequately describe individual claim elements. To be clear, the examiner is not looking for in haec verba support for the claim terms as written. However, many of the terms cannot be found in the specification as they appear in the claims. Nor does the originally filed specification adequately describe the claim terms using alternative language. In order to satisfy the test for written description, “one skilled in the art, reading the original disclosure, must immediately discern the limitation at issue in the claims” (emphasis added). Purdue Pharma L.P. v. Faulding Inc., 230 F.3d 1320, 2323 (Fed. Cir. 2000).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation " the apparatus is configured such that the adjusting results in a permanent repair of identified the one or more faulty components of the apparatus”. Examiner fails to see from the provided citations how “permanent repairs” can be adjusted if they are permanent, which means they can’t be adjusted, and thus is indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20, 23-28 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach [US2012/0196409] hereinafter Bach, in view of Chen et al. [US2010/0320565]. Or-Bach teaches 3D semiconductor device. Chen teaches wafer and method for improving yield rate of wafer.
Regarding claims 1 and 30, Bach teaches an apparatus [Bach abstract “…a semiconductor device…”], comprising:
a first semiconductor platform including a first memory [Bach paragraph 0015, first lines “…first transistor layer… a plurality of sequential cells”]; and
a second semiconductor platform stacked with the first semiconductor platform [Bach paragraph 0015, middle lines “…a second transistor layer overlaying the first transistor layer…”], the second semiconductor platform including a second memory [Bach paragraph 0015, last lines “…transistors of second transistor layer…”];
circuitry in communication with the first semiconductor platform and the second semiconductor platform [Bach paragraph 0114, first lines “…A possible fabrication method for constructing the programming circuitry in an Attic above the functional circuitry on the base silicon is by bonding a programming circuitry wafer on top of functional circuitry wafer using Through Silicon Vias…”], the circuitry:
identifying one or more faulty components of the apparatus [Bach paragraph 0201, last lines “…the defect can develop into a failure which may be detected during subsequent tests in the field…”], the identified one or more faulty components capable of including:
Bach fails to explicitly teach a bus that utilizes a first through-silicon via (TSV) in communication between the first semiconductor platform and the second semiconductor platform.
However, Chen does teach a bus that utilizes a first through-silicon via (TSV) in communication [Chen paragraph 0009, first lines “…a function of the TSV is generally categorized into four types: signal transmission, power delivery, thermal conduction, and input/output port connection…”] between the first semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of upper…layers via the TSVs…”] and the second semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of…lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”].
Bach and Chen are analogous arts in that they both deal with repairing failed TSV.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bach’s semiconductor platform with Chen’s detailed teachings of repairing failed TSV with spare TSV for the benefit of providing spare TSV during production to increase both yield and reliability [Chen paragraph 0010, middle lines “…the yield is increased and the reliability is enhanced, but an area of the wafer is increased as well…”].
a memory cell of at least one of the first memory or the second memory [Bach paragraph 0195, middle lines “…Examples of such include, but are not limited to, analog blocks, I/O, memory, and other blocks…” and paragraph 0249, middle lines “…When a bad block is detected, an entire new block would need to be crafted on the Repair Layer with Direct-Write e-Beam…” and paragraph 0178, all lines “…The idea is to tile the whole wafer with a dense pattern of memory cell, and then customize it using selective etching as before, and providing the required non-repetitive structures through an adjacent logic layer below or above the memory layer. FIG. 23A is a drawing illustration of a typical 6-transistor SRAM cell 2320, with its word line 2322, bit line 2324 and its inverse 2326. Such bit cell is typically densely packed and highly optimized for a given process…A four by four array 2332 may be defined through custom etching away the cells in channel 2334, leaving bit lines 2336 and word lines 2338 unconnected. These word lines 2338 may be then connected to an adjacent logic layer below that will have a word decoder 2350 in FIG. 23C that will drive them through outputs 2352. Similarly the bit lines may be driven by another decoder such as 2360 in FIG. 23D through its outputs 2362. A sense amplifier 2368 is also shown. A critical feature of this approach is that the customized logic can be provided from below or above in close vertical proximity to the area where it is needed assuring high performance customized memory blocks…"]; and
adjusting at least one aspect of the apparatus to repair the identified one or more faulty components including: the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0009, first lines “…a function of the TSV is generally categorized into four types: signal transmission, power delivery, thermal conduction, and input/output port connection…” and paragraph 0026, last lines “…inside wafers of upper and lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”], in response to the identification of the one or more faulty components of the apparatus that includes the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…after the wafer 600 has been manufactured and tested to find the failure of the TSV 605, a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604…”].
wherein the apparatus is configured such that the adjusting:
causes a change with respect to at least one of a first plurality of circuits in communication with the first TSV that is in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive…”(Where a first plurality of circuits is extremely broad and allows an anti-fuse to read on the claim language.)], and
causes a change with respect to at least one of a second plurality of circuits in communication with the first TSV that is in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035, all lines “…and the switching unit 609 is programmed to be conductive…”(Where a second plurality of circuits is extremely broad and allows switches to read on the claim language.)],
such that the identified one or more faulty components including the bus that utilizes the first TSV is repaired [Chen paragraph 0031, last lines “…The spare TSV 604 passes through the wafer 600 vertically, and is used to replace the failed TSV 603 or 605 when the TSV 603 or 605 has failed…”], by the bus utilizing a second TSV [Chen paragraph 0031, last lines “…The spare TSV 604…”] in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0026, last lines “…inside wafers of the upper layer and lower layers via the TSVs…” and paragraph 0007, first lines “…the die stack using the TSV technique for three-dimensional integration has a higher throughput in a wafer-to-wafer process than other processes in a bonding method…”], instead of the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0031, middle lines “…The TSV 603 passes through the wafer 600 vertically and is coupled to the circuit unit 601 via the front metal of the wafer 600. The TSV 605 passes through the wafer 600 vertically and is coupled to the circuit unit 602 via a front metal of the wafer 600. Hence, the circuit units 601 and 602 are capable of transmitting signals with circuit units (not shown) inside wafers of upper and lower layers via the TSVs 603 and 605 respectively…”], as a result of the change with respect to the at least one of the first plurality of circuits and the change with respect to the at least one of the second plurality of circuits [Chen paragraph 0035, all lines “…a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604…”].
Regarding claim 2, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a logic chip [Bach paragraph 0118, first lines “…Logic Blocks are constructed to implement programmable logic functions…”].
Regarding claim 3, as per claim 1, Bach teaches the apparatus is configured such that the circuitry is located on a same die as at least one of the first semiconductor platform or the second semiconductor platform [Bach paragraph 0134, last lines “…which the Through Silicon Via is continuing vertically through all the dies constructing a global cross-die connection. FIG. 9B provides an illustration of similar sized dies constructing a 3D system. 9B shows that the Through Silicon Via 404 is at the same relative location in all the dies constructing a standard interface…”].
Regarding claim 4, as per claim 1, Bach teaches the apparatus is configured such that the circuitry is located on a same die as a processor that is separate from the first semiconductor platform and the second semiconductor platform [Bach figure 24A, feature 2434 “BIST Controller” is external to the layers 2412 and 2402].
Regarding claim 5, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer in communication with an input/output pin [Bach paragraph 0017, first lines “…The selectively coupleable additional input can be a multiplexer. A programmable element can be provided to control said multiplexer…” and paragraph 0247, last lines “…Then the BIST controllers of each block can coordinate locally and decide which block should have its inputs and outputs coupled to Layer 1 through the Layer 1 multiplexers 3722 and 3724…”].
Regarding claim 6, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer, and the circuitry is programmable [Bach paragraph 0193, first lines “…It should be noted that if multiplexer controls 2641 and 2642 are reprogrammable as in using memory cells…”] at manufacture before run time [Bach paragraph 0201, first lines “…The exemplary embodiments discussed so far are primarily concerned with yield enhancement and repair in the factory prior to shipping a 3D IC to a customer…”]., in response to the identification of the one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”].
Regarding claim 7, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a multiplexer, and the circuitry is programmable [Bach paragraph 0193, first lines “…It should be noted that if multiplexer controls 2641 and 2642 are reprogrammable as in using memory cells…”] at run time [Bach paragraph 0189, last lines “…Similar repair approach can also assist systems that require self-healing ability at every power-up sequence through use of memory-based repair structures as described…”], in response to the identification of the one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”].
Regarding claim 8, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components of the apparatus [Bach paragraph 0182, middle lines “…In the repair cycle the logic cone that feeds the faulty FF is identified, the net-list for the circuit is analyzed, and the faulty logic cone is replicated on the Repair Layer using Direct-Write e-Beam technology to customize the uncommitted logic through writing VIA6, and the replicated output is fed down to the faulty FF from the Repair Layer replacing the original faulty logic cone…”], which includes at least a portion of a bank of the first memory that corresponds to a row address [Bach paragraph 0225, all lines “…An advantage of the addressing scheme of FIG. 63B is that a broadcast ready mode is available by addressing all of the rows and columns simultaneously and monitoring all of the column bit lines 3378. If all the column bit lines 3378 are logic-0, all of the ERROR2 signals are logic-0 meaning there are no bad logic cones present on Layer 2. Since field correctable errors will be relatively rare, this can save a lot of time locating errors relative to a scan flip-flop chain approach. If one or more bit lines is logic-1, faulty logic cones will only be present on those columns and the row addresses can be cycled quickly to find their exact addresses…”].
Regarding claim 9, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in a permanent repair of identified the one or more faulty components of the apparatus [Bach paragraph 0302, middle lines “…A programmable technology like, for example, fuses, antifuses, flash memory storage, etc., could be used to effect both factory repair and field repair…”(The examiner has determined that using a fuse is permanent repair.)].
Regarding claim 10, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in a non-permanent repair, utilizing a look-up table, of the identified one or more faulty components of the apparatus that includes one or more memory locations, such that the look-up table is utilized to substitute the one or more memory locations with one or more other memory locations [Bach paragraph 0121, first lines “…FIG. 6 is a drawing illustration of one possible implementation of a four input lookup table 600 ("LUT4") that can implement any combinatorial function of 4 inputs…”].
Regarding claim 11, as per claim 1, Bach and Chen teaches the apparatus is configured such that the identified one or more faulty components includes the first TSV of the bus [Bach paragraph 0284, first lines “…The interlayer interconnects may be TSVs or some other interlayer interconnect technology…” and paragraph 0183, last lines “…This allows full customization of all contact, metal and via layers of the Repair Layer…” and paragraph 0009, first lines “…a function of the TSV is generally categorized into four types: signal transmission, power delivery, thermal conduction, and input/output port connection…”].
Regarding claim 12, as per claim 1, Bach teaches the apparatus is configured such that the identified one or more faulty components includes at least one lane [Bach paragraph 0195, middle lines “…Examples of such include, but are not limited to, analog blocks, I/O, memory, and other blocks…”].
Regarding claim 13, as per claim 1, Bach teaches the apparatus is configured such that the adjusting includes reallocating one or more wire connections [Bach paragraph 0110, last lines “…A typical programmable connectivity array tile will have up to a few tens of metal strips to serve as connectivity for a Logic Block ("LB") described later…” and paragraph 0125, last lines “…For example, nothing limits the LB from being rotated 90 degrees with its inputs and outputs connecting to short vertical wires instead of short horizontal wires, or providing access to multiple long wires 724 in every tile…”].
Regarding claim 14, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components, utilizing one or more fuses [Bach paragraph 0302, middle lines “…A programmable technology like, for example, fuses, antifuses, flash memory storage, etc., could be used to effect both factory repair and field repair…”(The examiner has determined that using a fuse is permanent repair.)].
Regarding claim 15, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”], utilizing one or more spare memory resources in a stacked memory package including the first semiconductor platform and the second semiconductor platform [Bach paragraph 0161, middle lines “…In case LB (1,0,0) malfunctions, which can be found by testing, the corresponding LB (1,0,1) on the redundancy/repair layer can be programmed to replace it by turning off switch 1706 and turning on switches 1707, 1717, and 1716 instead…”], where a number of the one or more spare memory resources is communicated via a control bus [Bach paragraph 0297, middle lines “…The ability to fix defects in the factory with Repair Layers combined with the ability to automatically fix delayed defects (by masking them with three layer TMR embodiments or replacing faulty circuits with two layer replacement embodiments) allows the creation of much larger and more complex three dimensional systems than is possible with conventional two dimensional integrated circuit (IC) technology…” and paragraph 0182, middle lines “…This information is transmitted by BCC to the external tester, and is driving the repair cycle…”].
Regarding claim 16, as per claim 1, Bach teaches the apparatus is configured such that the adjusting results in the repair of the identified one or more faulty components of the apparatus [Bach paragraph 0236, middle lines “…the location of the faulty logic cone is determined with regards to its location in the logic design hierarchy. For example, if the faulty logic cone were located inside LFB 3410 then the BIST routine for only that block would be run on both Layer 1 and Layer 2. The results of the two tests determine which of the blocks (and by implication which of the logic cones) is functional and which is faulty…”], utilizing repair information on one or more repair actions that is communicated between a separate processor and the circuity [Bach paragraph 0182, middle lines “…During manufacturing, after the IC has been finalized to metal 5 of the repair layer, the chips on the wafer are powered up through a tester probe, the BIST is executed, and faulty FFs are identified. This information is transmitted by BCC to the external tester, and is driving the repair cycle…”].
Regarding claim 17, as per claim 1, Bach teaches the apparatus is configured such that the circuitry performs a self-test [Bach paragraph 0227, first lines “…Using some form of Built In Self Test (BIST) has the advantage of being self contained inside 3D IC…”] utilizing one or more patterns applied to one or more portions of at least one of the first semiconductor platform or the second semiconductor platform [Bach paragraph 0226, middle lines “…then automatic test pattern generated (ATPG) vectors may be used in a manner similar to the factory repair embodiments…”].
Regarding claim 18, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a built- in self-test (BIST) controlled utilizing signals that are independent of memory signals [Bach paragraph 0227, first lines “…Using some form of Built In Self Test (BIST) has the advantage of being self contained inside 3D IC…” and paragraph 0236, first lines “…n order to repair a 3D IC like 3D IC 3300 of FIG. 33A using the block BIST approach, the part is put in a test mode and the DATA1 and DATA2 signals are compared at each scan flip-flop 3200 on Layer 1 and Layer 2 and the resulting ERROR1 and ERROR2 signals are monitored as described in the embodiments above or possibly using some other method…”(The examiner has determined DATA and ERROR to be different signals and thus BIST ERROR signals are independent from memory DATA signals].
Regarding claim 19, as per claim 1, Bach teaches the apparatus is configured such that the adjusting is in connection with a write or read command [Bach paragraph 0261, first lines “…can be monitored in real time while the circuit is in normal operating mode…”], and the at least one aspect includes a configuration of a register that is adjusted in response to the write or read command [Bach paragraph 0230, first lines “…Present in LFB 3400 is Linear Feedback Shift Register (LFSR) circuit 3430 for generating pseudo-random input vectors for LFB 3400 in a manner well known in the art. In FIG. 34 one bit of LFSR 3430 is associated with each of the inputs 3402 of LFB 3400. If an input 3402 couples directly to a flip-flop (preferably a scan flip-flop similar to 3200) then that scan flip-flop may be modified to have the additional LFSR functionality to generate pseudo-random input vectors…”].
Regarding claim 20, as per claim 1, Bach teaches the apparatus is configured such that the identifying is performed by the circuitry, utilizing a loopback function and a linear feedback shift register (LFSR) [Bach paragraph 0230, first lines “…Present in LFB 3400 is Linear Feedback Shift Register (LFSR) circuit 3430 for generating pseudo-random input vectors for LFB 3400 in a manner well known in the art. In FIG. 34 one bit of LFSR 3430 is associated with each of the inputs 3402 of LFB 3400. If an input 3402 couples directly to a flip-flop (preferably a scan flip-flop similar to 3200) then that scan flip-flop may be modified to have the additional LFSR functionality to generate pseudo-random input vectors…”].
Regarding claim 23, as per claim 1, Bach teaches the apparatus is configured such that at least one of the first semiconductor platform or the second semiconductor platform, includes a plurality of TSV data buses that are divided into one or more groups each corresponding to at least a portion of a memory array of at least one of the first semiconductor platform or the second semiconductor platform [Bach paragraph 0144, first lines “…when the TSV patterns on top of each die are standardized in shape, with each TSV having either predetermined or programmable function…”].
Regarding claim 24, as per claim 1, Bach teaches the apparatus is configured such that the at least portion of a memory array includes a subarray of the memory array [Bach paragraph 0013, last lines “…semiconductor layer comprise repeating memory structure with sub structures defined by etching…” and paragraph 0173, all lines “…a section of a Gate Array terrain with a repeating transistor cell structure. The cell is similar to the one of FIG. 20C wherein the respective gate of the N transistors are connected to the gate of the P transistors. FIG. 20D illustrate an implementation of basic logic cells: Inv, NAND, NOR, MUX..”].
Regarding claim 25, as per claim 1, Bach teaches the apparatus is configured such that the subarray corresponds to a portion of the memory array corresponding to a row buffer [Bach paragraph 0010, middle lines “…the part also has a variety of input/output cells 2920, each comprising a bond pad 2922, an input buffer 2924, and a tri-state output buffer 2926…”].
Regarding claim 26, as per claim 1, Bach teaches the apparatus is configured such that access to the first memory is divided into one or more virtual channels addressed utilizing an address field [Bach paragraph 0267, first lines “…The row and column addresses are virtual addresses, since in a logic design the locations of the flip-flops will not be neatly arranged in rows and columns…”].
Regarding claim 27, as per claim 1, Bach teaches the apparatus is configured such that the circuit periodically performs error detection and error scrubbing during runtime [Bach paragraph 0214, last lines “…Cyclic Redundancy Checking may be employed. These methods all involve stopping system operation and entering a test mode. Other methods of monitoring possible error conditions in real time will be discussed below…” and paragraph 0280, middle lines “…The ability to fix defects in the factory with Repair Layers combined with the ability to automatically fix delayed defects (by masking them with three layer TMR embodiments or replacing faulty circuits with two layer replacement embodiments) allows the creation of much larger and more complex three dimensional systems…”].
Regarding claim 28, as per claim 1, Bach teaches the apparatus is configured such that the circuitry includes a timing control circuit that, during an initialization of the apparatus, measures to determine one or more delay properties of one or more interconnect structures, for adjusting a signal timing to align with one or more strobes [Bach paragraph 0185, all lines “…It should be noted that the repair flow just described can be used to correct not only static logic malfunctions but also timing malfunctions that may be discovered through the scan or BIST test. Slow logic cones may be replaced with faster implementations constructed from the uncommitted logic on the Repair Layer further improving the yield of such complex systems…”].
Regarding claim 31, as per claim 1, Chen teaches wherein the apparatus is configured such that changes are caused with respect to multiple of the first plurality of circuits and multiple of the second plurality of circuits, in response to the identification of the one or more faulty components of the apparatus that includes the bus that utilizes the first TSV in communication between the first semiconductor platform and the second semiconductor platform [Chen paragraph 0035-0036, all lines “…after the wafer 600 has been manufactured and tested to find the failure of the TSV 605, a voltage is then respectively applied to the two metal layers of the anti-fuse 607 in the present exemplary embodiment, so that the anti-fuse 607 is changed from the original on-state to the short circuit state and the switching unit 609 is programmed to be conductive. As a result, the spare TSV 604 replaces the failed TSV 605, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the TSV 603 and the spare TSV 604. However, after the wafer 600 has been manufactured and tested to find the failure of the TSV 603, then a voltage is respectively applied to the two metal layers of the anti-fuse 606 in the present exemplary embodiment, so that the anti-fuse 606 is changed from the original on-state to the short circuit state and the switching unit 608 is programmed to be conductive. Therefore, the spare TSV 604 replaces the failed TSV 603, and the circuit units 601 and 602 are still capable of transmitting signals with the circuit units inside the wafers of the upper and lower layers respectively via the spare TSV 604 and the TSV 605…”].
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach [US2012/0196409] hereinafter Bach, in view of Chen et al. [US2010/0320565], in view of Shirota et al. [US2009/0040856]. Or-Bach teaches 3D semiconductor device. Chen teaches wafer and method for improving yield rate of wafer. Shirota teaches semiconductor memory device changing refresh interval depending on temperature.
Regarding claim 21, as per claim 1, Bach and Chen fail to explicitly teach the apparatus is configured such that temperature-based refresh timing-related information is encoded for being conveyed to