DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/14/2025, 5/15/2025, 5/16/2025 and 4/14/2026 have been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first resistor as in claim 48 must be shown. Additionally, the snubber circuit as required by claim 49 (from its dependency on claim 47) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Claim Objections
Claims 45-54 are objected to because of the following informalities:
in claim 45, “the thyristor circuit” lacks antecedent basis.
in claim 46, “the thyristor circuit” lacks antecedent basis.
in claim 47, “the snubber circuit” lacks antecedent basis.
in claim 49, “the thyristor circuit” lacks antecedent basis.
in claim 50, “the thyristor circuit” lacks antecedent basis.
in claim 50, “the second varistor circuit” lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112a
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 48-49 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 48 depends from claim 47 which requires a snubber circuit, but claim 48 additionally requires the claimed first resistor electrically connected in series to a second varistor. As can be seen in the Figure 6, the original disclosure has support for a second varistor but does not disclose the claimed first resistor or snubber circuit. Applicant cannot further refine the invention after filing while retaining the filing date.
Claim 49 depends from claim 48 which depends from claim 47 which requires a snubber circuit, but claim 49 additionally requires an inductor electrically connected between a first node of the thyristor circuit and a second node corresponding to a junction of the first varistor and the second varistor. As can be seen in the Figure 6, the original disclosure has support for the claimed inductor but does not disclose the claimed snubber circuit. Applicant cannot further refine the invention after filing while retaining the filing date.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 40-45 and 50-52 are rejected under 35 U.S.C. 102a1 as being anticipated by Tahiliani (EP 0462694 A2).
With respect to claim 40, Tahiliani discloses an active energy absorber module (Fig. 1 10) comprising: first (Fig. 1 14) and second lines (Fig. 1 ground), the first and second lines comprising one of first and second power lines in a single phase power system (Fig. 1 single phase) and first and second phase lines in a multiple phase power system; first (Fig. 1 15) and second thyristors (Fig. 1 16) electrically connected between the first and second lines; and a first varistor (Fig. 1 12) electrically connected to at least one of the first (Fig. 1 14) and second thyristors between the first and second lines.
With respect to claim 41, Tahiliani discloses the active energy absorber module of claim 40, wherein the first varistor (Fig. 1 12) is connected in electrical series with each of the first and second thyristors (Fig. 1 4).
With respect to claim 42, Tahiliani discloses the active energy absorber module of claim 40, wherein the first and second thyristors comprise a thyristor circuit (Fig. 1 4) in which the first and second thyristors are electrically connected in an anti-parallel configuration.
With respect to claim 43, Tahiliani discloses the active energy absorber module of claim 40, wherein the first thyristor is configured to transition to a conductive state responsive to a first half of a voltage waveform (Fig. 1 Vo positive) and the second thyristor is configured to transition to a conductive state responsive to a second half of the voltage waveform (Fig. 1 Vo negative).
With respect to claim 44, Tahiliani discloses the active energy absorber module of claim 43, wherein the second thyristor (Fig. 1 16) is configured to transition to a nonconductive state (Fig. 1 16 off when Vo positive) responsive to the first half of a voltage waveform and the first thyristor (Fig. 1 16) is configured to transition to a nonconductive state (Fig. 1 16 blocking when Vo negative) responsive to a second half of the voltage waveform.
With respect to claim 45, Tahiliani discloses the active energy absorber module of claim 40, wherein the first varistor (Fig. 1 12) is electrically connected in series with the thyristor circuit (Fig. 1 4) between the first and second lines.
With respect to claim 50, Tahiliani discloses the active energy absorber module of claim 40, further comprising a trigger circuit (Fig. 1 21,CONTROL) electrically connected to the first and second thyristors.
With respect to claim 51, Tahiliani discloses the active energy absorber module of claim 50, wherein the trigger circuit comprises: a comparison circuit (Fig. 1 CONTROL compares Vo to Vp) configured to receive a voltage level signal (Fig. 1 Vo) and a voltage reference signal (Fig. 2 Vp) and to output an overvoltage trigger signal (Fig. 1 output of comparison in CONTROL) responsive to the voltage level signal exceeding the voltage reference signal (Fig. 2 Vc decreases due to triggering at time 10-4).
With respect to claim 52, Tahiliani discloses the active energy absorber module of claim 51, wherein the trigger circuit further comprises: a gate trigger circuit (Fig. 1 23,24) configured to generate a gate trigger signal (Fig. 1 output of 23,24 to 15,16) responsive to the overvoltage trigger signal, the gate trigger signal being received by the first and second thyristors and causes at least one of the first and second thyristors to conduct current.
Claim(s) 40-49 and 55 are rejected under 35 U.S.C. 102a1 as being anticipated by Chadwick (US 4,475,139).
With respect to claim 40, Chadwick discloses an active energy absorber module comprising: first (Fig. 1 14) and second (Fig. 1 15) lines, the first and second lines comprising one of first and second power lines in a single phase power system (column 1, lines 30-40 ) and first and second phase lines in a multiple phase power system; first and second thyristors (Fig. 1 11A,12A) electrically connected between the first and second lines; and a first varistor (Fig. 1 22B) electrically connected to at least one of the first and second thyristors between the first and second lines.
With respect to claim 41, Chadwick discloses the active energy absorber module of claim 40, wherein the first varistor (Fig. 1 22B) is connected in electrical series with each of the first and second thyristors (Fig. 1 11A,12A).
With respect to claim 42, Chadwick discloses the active energy absorber module of claim 40, wherein the first and second thyristors comprise a thyristor circuit (Fig. 1 10) in which the first and second thyristors are electrically connected in an anti-parallel configuration.
With respect to claim 43, Chadwick discloses the active energy absorber module of claim 40, wherein the first thyristor (Fig. 1 11A) is configured to transition to a conductive state responsive to a first half (Fig. 1 voltage 14-15 is negative) of a voltage waveform and the second thyristor is configured to transition to a conductive state responsive to a second half (Fig. 1 voltage 14-15 is positive) of the voltage waveform.
With respect to claim 44, Chadwick discloses the active energy absorber module of claim 43, wherein the second thyristor (Fig. 1 12A) is configured to transition to a nonconductive state responsive to the first half (Fig. 1 voltage 14-15 is negative) of a voltage waveform and the first thyristor (Fig. 1 11A) is configured to transition to a nonconductive state responsive to a second half (Fig. 1 voltage 14-15 is positive) of the voltage waveform.
With respect to claim 45, Chadwick discloses the active energy absorber module of claim 40, wherein the first varistor (Fig. 1 22B) is electrically connected in series with the thyristor circuit (Fig. 1 11A,12A) between the first and second lines.
With respect to claim 46, Chadwick discloses the active energy absorber module of claim 40, further comprising a snubber circuit (Fig. 1 20A,21A) electrically connected in parallel with the thyristor circuit.
With respect to claim 47, Chadwick discloses the active energy absorber module of claim 40, wherein the snubber circuit comprises a resistor (Fig. 1 20A) and a capacitor (Fig. 1 21A) electrically connected in series.
With respect to claim 48, Chadwick discloses the active energy absorber module of claim 47, further comprising a first resistor (Fig. 1 20B) electrically connected in series to a second varistor (Fig.1 22C) between the first and second lines.
With respect to claim 49, Chadwick discloses the active energy absorber module of claim 48, further comprising an inductor (Fig.1 16) electrically connected between a first node (Fig. 1 27) of the thyristor circuit (Fig. 1 11A,12A,26) and a second node (Fig. 1 node 22B-22C) corresponding to a junction of the first varistor and the second varistor.
With respect to claim 55, Chadwick discloses the active energy absorber module of claim 40, further comprising a bypass circuit (Fig. 1 26) coupled to a circuit (Fig. 1 10,22A-C,16) comprising the first and second thyristors and first varistor between the first and second lines.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 53-54 are rejected under 35 U.S.C. 103 as being unpatentable over Tahiliani (EP 0462694 A2) in view of Politis (US 2016/0276821).
With respect to claim 53, Tahiliani discloses the active energy absorber module of claim 52, and remains silent as to implementing optical isolation, which was well known before the effective filing date of the claimed invention.
Politis discloses wherein the trigger circuit further comprises: an optical isolation circuit (Fig. 32 738) connected between the comparison circuit (Fig. 32 734) and the thyristor circuit (Fig. 32 TH1,TH2) to provide electrical isolation between the comparison circuit and the thyristor circuit. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the trigger circuit further comprises: an optical isolation circuit connected between the comparison circuit and the gate trigger circuit configured to provide electrical isolation between the comparison circuit and the gate trigger circuit, in order to protect the sensitive control electronics from the high voltage circuit and prevent false triggers.
With respect to claim 54, Tahiliani in view of Politis make obvious the active energy absorber module of claim 52, further comprising: at least one electrical wire (Fig. 20 232B) extending through a wire port (Fig. 20 282) and electrically connecting at least one of the first and second thyristors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement at least one electrical wire extending through a wire port and electrically connecting at least one of the first and second thyristors to the gate trigger circuit, in order to provide access of the gate control signal while maintaining the seal of the active energy absorber module to protect it from the environment.
Claim(s) 53 is rejected under 35 U.S.C. 103 as being unpatentable over Tahiliani (EP 0462694 A2) in view of Zeng (CN 204578516).
With respect to claim 53, Tahiliani discloses the active energy absorber module of claim 52 as set forth above, and remains silent as to implementing optical isolation which was well known before the effective filing date of the claimed invention.
Zeng discloses wherein the trigger circuit further comprises: an optical isolation circuit (Fig. 1 102) connected between the input (Fig. 1 1,2) circuit and the gate trigger circuit (Fig. 1 100) configured to provide electrical isolation between the comparison circuit and the gate trigger circuit. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the trigger circuit further comprises: an optical isolation circuit connected between the comparison circuit and the gate trigger circuit configured to provide electrical isolation between the comparison circuit and the gate trigger circuit, in order to provide access of the gate control signal while maintaining the seal of the active energy absorber module to protect it from the environment.
Claim(s) 54 is rejected under 35 U.S.C. 103 as being unpatentable over Tahiliani (EP 0462694 A2) in view of Zeng (CN 204578516) and further in view of Zhao (CN 104377673).
With respect to claim 54, Tahiliani in view of Zeng make obvious the active energy absorber module of claim 52 as set forth above, and remain silent as to implementing a wire port, which was well known before the effective filing date of the claimed invention.
Zhao discloses implementing at least one electrical wire (Fig. 4 wire to PE through 424) extending through a wire port (Fig. 4 424). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement at least one electrical wire extending through a wire port and electrically connecting at least one of the first and second thyristors to the gate trigger circuit, in order to provide access of the gate control signal while maintaining the seal of the active energy absorber module to protect it from the environment.
Claim(s) 55-59 are rejected under 35 U.S.C. 103 as being unpatentable over Tahiliani (EP 0462694 A2) in view of Kamel (US 7,433,169).
With respect to claim 55, Tahiliani discloses the active energy absorber module of claim 40 as set forth above, and does not disclose a bypass circuit. The use of bypass circuits in active energy absorber modules was known before the effective filing date of the claimed invention.
Kamel discloses a bypass circuit (Fig. 3 180). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a bypass circuit coupled to a circuit comprising the first and second thyristors and first varistor between the first and second lines, in order to prevent catastrophic failure of the device during high overcurrent and overheating conditions, while maintaining protection of the line.
With respect to claim 56, Tahiliani in view of Kamel make obvious the active energy absorber module of claim 55, wherein the bypass circuit comprises a switch (Fig. 3 180) operable to transition from an open state (Fig. 3 180) to a closed state (Fig. 4 180A) responsive to thermal energy (Fig. 4 180 melted).
With respect to claim 57, Tahiliani in view of Kamel make obvious the active energy absorber module of claim 56, wherein the switch comprises a meltable member (Fig. 3 180) configured to transition from a solid form to a liquid form responsive to a temperature of the meltable member exceeding a melting point temperature.
With respect to claim 58, Tahiliani in view of Kamel make obvious the active energy absorber module of claim 57, wherein the meltable member is configured to bridge terminals (Fig. 3 130,129) of the switch responsive to transitioning to the liquid form causing the switch to transition to the closed state (Fig. 4 180A).
With respect to claim 59, Tahiliani in view of Kamel make obvious the active energy absorber module of claim 56, wherein the switch is configured to divert current away from the circuit (Fig. 4 110) when in the closed state.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 40-42, 45-47 and 50-53 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,1,1,1,7,7,4,5,5 and 6, respectively, of U.S. Patent No. 10,447,026. Although the claims at issue are not identical, they are not patentably distinct from each other because the application has broadened the claims of the patent which anticipates the cited claims by claiming all the limitations of the first and second lines, first and second thyristors, varistor, snubber circuit, trigger circuit, comparison circuit, gate trigger circuit and optical isolation circuit.
Claims 40-42, 45-47 and 50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7, respectively, of U.S. Patent No. 11,881,704. Although the claims at issue are not identical, they are not patentably distinct from each other because the application has merely broadened the claim language of the patent, and the patent anticipates all the claimed limitations of the cited claims such as the claimed first and second lines, first and second thyristors, varistor, snubber circuit and trigger circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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