Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/24/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 01/24/2025. These drawings are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Kundu et al. (USPGPUB No. 2023/0281053 A1, hereinafter referred to as Kundu) in view of Narayanam et al. (USPGPUB No. 2021/0194672 A1, hereinafter referred to as Narayanam) and further in view of Vorbach et al. (USPGPUB No. 2012/0137075 A1, hereinafter referred to as Vorbach).
Referring to claim 1, Kundu discloses a compute integrated circuit {“network protocol stack 100”, see Fig. 1 [0068]}, the compute integrated circuit comprising {said “stack 100 corresponds to… provide 5G-NR service” ([0068]} which includes processing resources ([0001]):
a bus interface {“Serial Link and Ethernet”, see Fig. 10a [0202]};
a plurality of registers {“register file 2058” that configures more than one register, see Fig. 20D [0353]};
a manager configured to {“GPGPU cores 2058”, see Fig. 20D [0353]}:
receive, from an external device via the bus interface {“point-to-multipoint transmission”, Fig. 37 [0481], last 4 lines}, a multicast read command for data in a requested register set {“register file 2058” as a register set “allocates an entry for each uop in one of two uop queues”, see Fig. 23 [0365]};
and in response to determining, based on the plurality of register set configurations {“allocator/register renamer 2340 [determining] renames logic registers onto entries in a register file”, [0365], see Fig. 23}, that the plurality of registers include a register {include a register specified among “128-bit wide entries”, Fig. 23 [0367], last 4 lines} in the requested register set {“register file 2058 is very low latency.”, see Fig. 20d [0356]},
Kundu does not appear to explicitly disclose wherein the compute integrated circuit for a cryptocurrency miner;
a plurality of register set configurations, wherein each register set configuration specifies a register of the plurality of registers that is part of an associated register set and a bit delay for the register in the associated register set;
However, Narayanam discloses wherein the compute integrated circuit {“transactions on the ledger may be sequenced and cryptographically linked together” ([0041]) via a processor including “The processor and the storage medium may reside in an application specific integrated circuit” ([0120]) or a “[compute] module may be implemented as a hardware circuit comprising custom very large-scale integration (VLSI) circuits” ([0189], 2nd sentence)} for a cryptocurrency miner {“transactions on the ledger may be sequenced and cryptographically linked together” ([0041]) by a integrated circuit above as “blockchains, [crypto currency] miners may be rewarded with value (e.g., coins, etc.) for correctly mining a block”, see Fig. 3C, [0088], last sentence};
a plurality of register set configurations {“allows chaincode to specify endorsers for” set configurations [0038]}, wherein each register set configuration specifies a register {“be simply an indexed view into the chain's transaction log [at the storage location blockchain],” [0042]} of the plurality of registers {“can run on the same physical server [database file]” [0039]} that is part of an associated register set {“[the claimed values latest values of the keys]” therefore be regenerated from the chain at any time.” [0042]} and a bit delay {“at any time” including after the claimed specified latency [0042]} for the register in the associated register set {“be simply an indexed view into the chain's transaction log [at the associated register set/storage location blockchain],” [0042]};
Kundu and Narayanam are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kundu and Narayanam before him or her, to modify Kundu’s “network protocol stack 100” (see Fig. 1 [0068]) incorporating Narayanam’s “blockchain architecture configuration 200” (see Fig. 2a, [0068], 1st sentence).
The suggestion/motivation for doing so would have been to implement Blockchain frameworks such as Hyperledger Fabric provide an enterprise-grade permissioned distributed ledger technology (Narayanam [0043], 1st sentence) to make these chaincode interactions efficient, the latest values of the keys may be stored in a state database (Narayanam [0042]).
Therefore, it would have been obvious to combine Chrysos with Gray to obtain the invention as specified in the instant claim(s).
Neither Kundu or Narayanam appears to explicitly disclose return data from the register in the requested register set to the external device via the bus interface per the bit delay specified for the register in the requested register set;
However, Vorbach discloses return data from the register {“TCM memories may also be connected”, see Fig. 8, [0467], 1st sentence} in the requested register set {“A reference register (0704) comprises the TIMER-THRESHOLD which may be set to a specific value right after reset of the core”, see Fig. 7, [0696], 1st sentence} to the external device {[external device] cache miss, the address is looked up in the ATAG memory”, see Figs. 6 and 7 [0702]} via the bus interface per the bit delay specified {“value of the access-statistics-timer exceeds a specific maximum [bit delay] threshold before reset.”, see Fig. 6, [0152], 2nd sentence} for the register in the requested register set {“spilled register variables, constants and scratch data benefit from low access latencies”, [0526], last sentence}.
Kundu/Narayanam and Vorbach are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kundu/Narayanam and Vorbach before him or her, to modify Kundu/Narayanam’s device incorporating Vorbach “TCM memories” (see Fig. 14, [0407]).
The suggestion/motivation for doing so would have been to implement/using TAGs for locking is more efficient than explicit locking code, as the locking might be managed completely in hardware, which is faster than software locking (Vorbach [0328], 1st sentence).
Therefore, it would have been obvious to combine Vorbach Kundu/Narayanam to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Kundu discloses wherein:
one or more fields of the multicast read command {“opcode and corresponding data and control fields”, [0363]} identify the requested register set {managers “fast scheduler 2302 of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler 2304 and simple floating point scheduler 2306 may schedule once per main processor clock cycle.”, see Fig. 23 [0365], last 6 lines};
the manager is configured to select {managers “fast scheduler 2302 of at least one embodiment may select on each half of main clock cycle while slow/general floating point scheduler 2304 and simple floating point scheduler 2306…”, see Fig. 23 [0365], last 6 lines}, based on the one or more fields of the multicast read command {“opcode and corresponding data and control fields”, [0363]}, the register set configuration for the requested register set {“has a dedicated high-bandwidth register file and associated independent thread-state”, [0414], see Fig. 29a};
Vorbach discloses identify, from the selected register set configuration {identified “multiple ALU-Blocks in an array with pipeline stages between each row of ALU-Blocks”, [0024], 1st sentence}, the register in the requested register set {“pipeline stages between each row of [register set] ALU-Blocks” ([0024], 1st sentence) “whereas the structure may be understood as a MIMD (Multiple Instruction, Multiple Data) machine” ([0024], last sentence)} and the bit delay for the register in the requested register set {“value of the access-statistics-timer exceeds a specific maximum [bit delay] threshold before reset.”, see Fig. 6, [0152], 2nd sentence}.
As per claim 3, the rejection of claim 1 is incorporated and Vorbach discloses wherein the bit delay for the register in the requested register set specifies a number of bits {“value of the access-statistics-timer exceeds a specific maximum [bit delay] threshold before reset.”, see Fig. 6, [0152], 2nd sentence} after receipt of the multicast read command {“address request is broadcasted via all direct edges to the children of the node”, see Fig. 5 [0717]} to wait before {“the allocation unit may return a wait signal until a bus becomes available”, see Fig. [0725], last sentence} returning the data to the external device via the bus interface {“TCM memories may also be connected”, see Fig. [0467], 1st sentence}.
As per claim 4, the rejection of claim 1 is incorporated and Kundu discloses wherein each register set configuration specifies the bit delay at 4-bit granularity {“half-precision floating point” which has operations at 8-bit, 16-bit which logically includes 4-bit, [0138]}.
As per claim 5, the rejection of claim 1 is incorporated and Narayanam discloses wherein the manager is configured to determine that the multicast read command is directed {“generate a block and broadcast the block to the blockchain peers participating the blockchain network”, [0045], 1st sentence} to the compute integrated circuit before returning the data from the register in the requested register set {“broadcasts the transaction proposal and response within a [return] transaction message to the ordering node 284”, see Fig. 2B [0078], 1st sentence}.
As per claim 6, the rejection of claim 1 is incorporated and Kundu discloses wherein the plurality of register set configurations are stored in the plurality of registers {claimed configurations “performs integer operations… floating point operations” to name a few, see Fig. 23 [0367]}.
Referring to claims 7-15 are device claims reciting claim functionality corresponding to the apparatus claims of claims 1-6 respectively, thereby rejected under the same rationale as claims 1-6 recited above, inter alia, per claim 9, incorporating the rejection of claim 7, Narayanam further discloses wherein the miner controller is configured to program {“where the [programmable] algorithm rewards miners”, see Fig. 3c [0087], last two sentences}, prior to issuing the single multicast read command {“generate a block and broadcast the block to the blockchain peers participating the blockchain network”, [0045], 1st sentence}, each compute integrated circuit {“The processor and the storage medium may reside in an application specific integrated circuit” ([0120]) or a “[compute] module may be implemented as a hardware circuit comprising custom very large-scale integration (VLSI) circuits” ([0189], 2nd sentence} such that its register set configuration for the requested register set {“peer must request all the previous [register set] blocks before it could validate transactions from the currently received block. However, in the example embodiments, due to partial ordering, a blockchain peer can request for only those blocks on which the transactions in the current block depend”, see Fig. 1b, [0064], last two sentences} specifies the bit delay for its register {“hash validation may take a [bit delay] long time since it needs to wait for many immediate previous blocks to be received”, see Fig. 1b [0058], last two sentences} in the requested register set {“[requested register set] All blocks in a slot may not be validated in parallel due to limited number of processors each peer possesses”, see Fig. 1b [0058], last sentence}.
As per claim 10, the rejection of claim 1 is incorporated and Narayanam discloses wherein the miner controller is configured to program {“where the [programmable] algorithm rewards miners”, see Fig. 3c [0087], last two sentences}, prior to issuing the single multicast read command {“generate a block and broadcast the block to the blockchain peers participating the blockchain network”, [0045], 1st sentence};
Vorbach discloses each compute integrated circuit with a different bit delay for its register {“value of the access-statistics-timer exceeds a specific maximum [bit delay] threshold before reset.”, see Fig. 6, [0152], 2nd sentence} in the requested register set such that the compute integrated circuits return data from their respective register {“Each ALU may execute a different instruction on a different set of data” returning data as configured “while multiple data words are streamed through the ALUs” ([0025], 2nd sentence)} in the requested register set during non-overlapping periods {“[non-overlapping] locks can be classified by what happens when the lock strategy prevents progress of a thread”, [0168], 1st sentence}.
Referring to claims 16-20 are method claims reciting claim functionality corresponding to the apparatus claims of claims 1-6 respectively, thereby rejected under the same rationale as claims 1-6 recited above, inter alia, per claim 19, incorporating the rejection of claim 18, Narayanam further discloses comprising:
programming each {“where the [programmable] algorithm rewards miners”, see Fig. 3c [0087], last two sentences} compute integrated circuit in the plurality of compute integrated circuits {“The processor and the storage medium may reside in an application specific integrated circuit” ([0120]) or a “[compute] module may be implemented as a hardware circuit comprising custom very large-scale integration (VLSI) circuits” ([0189], 2nd sentence} with a multicast address {“public key may be distributed publicly to serve as an address to receive messages from other users, e.g., an IP address or home address”, see Fig. 7D, [0165]};
wherein the first multicast read command is directed to the multicast address {“also permit a tracing through the blockchain back to the original file”, see Fig. 7D [0152], last two sentences}; and
wherein the second multicast read command is directed to the multicast address {“ tracking confirms the chain-of-custody of the [addressed] file throughout the entire blockchain”, see Fig. 7D [0152], last two sentences}.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “register set configuration”, “bus interface”, or “integrated circuit”: US 12107952 B2, US 20240062170 A1, US 11301481 B2, US 20210182849 A1, US 10938578 B2, US 20200341934 A1, US 10673617 B1, US 20190081793 A1, US 10121143 B1, AND US 20180204111 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights