DETAILED ACTION
This Office action is in response to the application filed on 24 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, 13-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paparrizos et al. (US 2014/0203761; hereinafter “Paparrizos”).
In re claims 1 and 16, Paparrizos discloses a buck boost converter and its corresponding method of its use (see Fig. 3), comprising:
an input pin (102), configured to receive an input voltage (Vin);
a first switch pin (304a), 1) configured to receive the input voltage via a first power switch (HS1) and 2) coupled to a reference ground via a second power switch (LS1);
a first bootstrap pin (node between D1, C1), configured to provide a first bootstrap voltage to the first power switch (via driver 308a as shown);
an output pin (106), configured to provide an output voltage (Vsys);
a second switch pin (304b), coupled to 1) the reference ground via a third power switch (LS2) and 2) the output pin via a fourth power switch (HS2);
a second bootstrap pin (node between D2, C2), configured to provide a second bootstrap voltage to the fourth power switch (via driver 308b as shown); and
a control circuit (remaining circuit components of Fig. 3), having a bootstrap refresh circuit (314) and a control signal generator (including 312a/b, 316a/b, 318a/b); wherein:
when the buck boost converter operates at a pass through mode (Fig. 6: any of the four operation modes (1st column) may be considered a pass through mode in that one of the switch pairs (i.e., either HS1/LS1 or HS2/LS2) are fixed ON/OFF to allow pass-through of current through the respective side of the buck-boost converter; see also Figs. 7A-7D), the bootstrap refresh circuit is configured to periodically generate a refresh clock signal (314a, 314b), and the control signal generator is configured to generate a first control signal (HS1 gate signal), a second control signal (LS1 gate signal), a third control signal (LS2 gate signal), and a fourth control signal (HS2 gate signal) in response to the refresh clock signal (logic gates 316/318 receive refresh clock 314 signals) and a mode indicate signal (not explicitly shown, see, e.g., [0053]: “the configuration detector 216 may assert various control signals (not shown) that can inform the buck boost circuit 212 to configure for forward boost mode” (emphasis added), and similar operation for other modes as explained in [0054]-[0056]), to respectively control the first power switch, the second power switch, the third power switch, and the fourth power switch ([0040], [0044]).
In re claims 7 and 9, Paparrizos discloses a buck boost converter (Fig. 3), comprising:
an input pin (102), configured to receive an input voltage (Vin);
a first switch pin (304a), 1) configured to receive the input voltage via a first power switch (HS1) and 2) coupled to a reference ground via a second power switch (LS1);
a first bootstrap pin (node between D1, C1 and 308a), configured to provide a first bootstrap voltage to the first power switch (voltage on C1 provided to gate of HS1 via driver 308a);
an output pin (106), configured to provide an output voltage (Vsys);
a second switch pin (304b), coupled to 1) the reference ground via a third power switch (LS2) and 2) the output pin via a fourth power switch (HS2);
a second bootstrap pin (node between D2, C2 and 308b), configured to provide a second bootstrap voltage to the fourth power switch (voltage on C2 provided to gate of HS2 via driver 308b); and
a control circuit (remaining circuit components of Fig. 3), having a bootstrap manage circuit (314, 308a/b, 310a/b, 312a/b, 316a/b, 318a/b), coupled to the first switch pin (304a), the first bootstrap pin (node between D1, C1), the second switch pin (304b), and the second bootstrap pin (node between D2, C2), to monitor a undervoltage condition of the first bootstrap voltage and the second bootstrap voltage ([0109]: the refresh circuit 314 monitors events including insufficient charge (equivalent to undervoltage) on the boot capacitors C1/C2),
wherein when at least one of the first bootstrap voltage and the second bootstrap voltage has the undervoltage condition, the bootstrap manage circuit is configured to control the first power switch to fourth power switch to operate at a refresh mode (id.: refresh circuit 314 generates the refresh pulses 314a/b in response to the undervoltage event on C1 or C2; the refresh pulses control the four power switches via the logic gates 316/318 in Fig. 3: see [0044]).
In re claims 2 and 15, Paparrizos discloses wherein the control signal generator is configured to control the first power switch to the fourth power switch to operate at a refresh mode in response to the refresh clock signal (Fig. 3, [0044], [0109]: logic gates 316, 318 receive refresh clock pulses 314a/b to control the four power switches).
In re claims 3, 10 and 17, Paparrizos discloses wherein the refresh mode comprises:
the first power switch and the fourth power switch are controlled to be OFF, and the second power switch and the third power switch are controlled to be ON for a first time period ([0110]-[0111]); and
then the first power switch and the fourth power switch are controlled to be ON, and the second power switch and the third power switch are controlled to be OFF for a second time period (as shown, e.g., in Fig. 7A for the forward boost mode of Fig. 6).
In re claim 4, Paparrizos discloses wherein:
when the buck boost converter operates at the pass through mode and an undervoltage condition occurs at least one of the first bootstrap voltage and the second bootstrap voltage ([0109]), the bootstrap refresh circuit is configured to generate the refresh clock signal for at least one switching cycle, to control the first power switch to the fourth power switch to operate at the refresh mode for at least one switching cycle ([0111]-[0112]: the pulse width of the refresh pulses is considered as one switching cycle).
In re claim 5, 11 and 18, Paparrizos discloses wherein:
the buck boost converter is configured to judge again whether the first bootstrap voltage and the second bootstrap voltage are still under the undervoltage condition after the first power switch to the fourth power switch operating at the refresh mode for at least one switching cycle ([0109]: that the refresh pulses are “event-driven” is understood to mean that the undervoltage/insufficient charge event is continuously monitored):
if at least one of the first bootstrap voltage and the second bootstrap voltage is still under the undervoltage condition, the bootstrap refresh circuit is configured to continue generating the refresh clock signal, to control the first power switch to the fourth power switch to continue operating at the refresh mode, until both the first bootstrap voltage and the second bootstrap voltage exit from the undervoltage condition ([0109]-[0111]: “event-drive” is understood to mean that the refresh pulses will be generated until the undervoltage/insufficient charge event no longer exists).
In re claim 6, 13-14 and 20, Paparrizos discloses wherein the mode indicate signal comprises at least one of:
a buck indicate signal, a boost indicate signal, a buck-boost indicate signal and a pass through indicate signal (see operating modes of Fig. 6; see [0053]-[0056]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paparrizos in view of Guerra et al. (US 2023/0246550; hereinafter “Guerra”).
In re claims 8 and 12, Paparrizos discloses the invention according to claims 7 and 9 as explained above and further discloses wherein the bootstrap manage circuit comprises: the bootstrap refresh circuit (Fig. 3: 314), configured to generate the refresh clock signal (314a/b)
However, Paparrizos does not disclose a first compare circuit, configured to generate a first comparison signal in response to a voltage at the first switch pin, the first bootstrap voltage, and a first threshold voltage; a second compare circuit, configured to generate a second comparison signal in response to a voltage at the second switch pin, the second bootstrap voltage, and a second threshold voltage; and the refresh clock signal being generated in response to the first comparison signal or the second comparison signal.
Whereas Guerra discloses a buck-boost boot refresher circuit (see Fig. 9) including first and second compare circuits (908_1, 908_2) to generate comparison signals (C1, C2) in response to voltages across the bootstrap capacitors (CB1, CB2, detected by circuits 906_1, 906_2) and respective threshold voltages (Vth1, Vth2) in order to activate the bootstrap refresh mode when the voltage across either of the bootstrap capacitors falls below the threshold ([0069]-[0072]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter of Paparrizos by including a first compare circuit, configured to generate a first comparison signal in response to a voltage at the first switch pin, the first bootstrap voltage, and a first threshold voltage; a second compare circuit, configured to generate a second comparison signal in response to a voltage at the second switch pin, the second bootstrap voltage, and a second threshold voltage; and the refresh clock signal being generated in response to the first comparison signal or the second comparison signal in order to implement the event-driven bootstrap refresh process according to the voltage across either of the bootstrap capacitors falling below the threshold as taught by Guerra.
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 19, the closest prior art in Paparrizos discloses the invention according to claim 17 as explained above, but does not further disclose the step of: when the undervoltage condition occurs at least one of the first bootstrap voltage and the second bootstrap voltage, turning on the second power switch after a first time length since the first power switch and the fourth power switch are turned off, and turning on the third power switch after a second time length since the first power switch and the fourth power switch are turned off.
That is, in Paparrizos, there is no teaching of respective, first and second time lengths between turning OFF the first and fourth power switches, and respectively turning ON the second power switch (first time length) and the third power switch (second time length). Further the additional prior art on record does not teach such a feature, and thus there is no obvious suggestion to modify Paparrizos in a manner that would result in the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2014/0217959 discloses a HYBRID BOOTSTRAP CAPACITOR REFRESH TECHNIQUE FOR CHARGER/CONVERTER.
US 2017/0288550 discloses an ULTRASONIC CONTROL SYSTEM AND METHOD FOR A BUCK-BOOST POWER CONVERTER in which switch control is configured to, when an on time of the second switch becomes less than a specified entry value, force the third switch to generate boot refreshing pulses with an on time of a specified duration value at a rate more than a specified frequency, and when an on time of the third switch becomes less than the specified entry value, force the second switch to generate boot refreshing pulses with an on time of the specified duration value at the rate more than the specified frequency.
US 2018/0109179 discloses a BOOTSTRAP CIRCUIT FOR DC/DC CONVERTER including bootstrap refresh in a buck-boost converter.
US Patent 10,135,340 discloses Pass Through Regulation Of Buck-boost Regulator.
US 2019/0238051 discloses a DRIVING CIRCUIT AND METHOD FOR BUCK-BOOST CONVERTER WITH BOOTSTRAP VOLTAGE REFRESH.
US 2026/0025073 discloses a METHOD FOR CONTROLLING BUCK-BOOST CIRCUIT, POWER CONVERSION DEVICE, ENERGY STORAGE DEVICE, AND STORAGE MEDIUM including bootstrap refresh during a pass-through mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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