DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on January 24, 2025.
Drawings
3. The drawings were received on January 24, 2025. These drawings are accepted.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-6 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2012/0086418).
Regarding claim 1, Lee et al discloses an integrated circuit (i.e. circuit of Figure 3), comprising:
a switching control pin (Fig. 3, input terminal of current balance circuit 14 connected to phase OFF signal) configured to receive a control signal (Fig. 3, phase OFF signal);
a first power unit (Fig. 3, 1st phase power stage 12) having at least one power switch (Fig. 3, power switch within 1st phase power stage 12) (See ¶[0004]), wherein the first power unit (Fig. 3, 1st phase power stage 12) is configured to provide a first current (Fig. 3, current I1 outputted from power stage 12) (See ¶[0004]);
a second power unit (Fig. 3, 2nd phase power stage 22) having at least one power switch (Fig. 3, power switch within 2nd phase power stage 22) (See ¶[0004]), wherein the second power unit (Fig. 3, 2nd phase power stage 22) is configured to provide a second current (Fig. 3, current I2 outputted from power stage 22) (See ¶[0004]) greater than the first current (Fig. 3, current I1 outputted from power stage 12) (i.e. either current I1 or I2 can be higher than the other since current balance circuit 14 receives signals indicative of the current signals, and generates to current balance signal so that current I1 and I2 are balanced. (See ¶[0004]);
a driving control circuit (Fig. 3, circuit of current balance circuit 14, 1st phase pwm controller 11, 2nd phase pwm controller 21, and soft shutdown control circuit 15) configured to provide a first driving signal (Fig. 3, signal PWM1) to the first power unit (Fig. 3, 1st phase power stage 12) in response to the control signal (Fig. 3, phase OFF signal), and to provide a second driving signal (Fig. 3, signal PWM2) to the second power unit (Fig. 3, 2nd phase power stage 22) in response to the control signal (Fig. 3, phase OFF signal);
a first current sense circuit (Fig. 3, circuit generating current I1 from 1st phase power stage 12) configured to provide a first current sense signal (Fig. 3, current I1) indicating the first current provided by the first power unit (Fig. 3, 1st phase power stage 12); and
a second current sense circuit (Fig. 3, circuit generating current I2 from 2nd phase power stage 22) configured to provide a second current sense signal (Fig. 3, current I2) indicating the second current provided by the second power unit (Fig. 3, 1st phase power stage 12).
Regarding claim 2, Lee et al further discloses wherein each of the first power unit (Fig. 3, 1st phase power stage 12) and the second power unit (Fig. 3, 2nd phase power stage 22) comprises:
a first switch (Fig. 2A, top transistor) having a first terminal (Fig. 2A, terminal of top transistor connected to source Vin), a second terminal (Fig. 2A, terminal of top transistor connected to inductor and bottom transistor) and a control terminal (Fig. 2A, gate terminal of top transistor), wherein the first terminal (Fig. 2A, terminal of top transistor connected to source Vin) of the first switch (Fig. 2A, top transistor) is configured to receive an input voltage (Fig. 2A, source Vin) (See ¶[0004]); and
a second switch (Fig. 2A, bottom transistor) having a first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor), a second terminal (Fig. 2A, terminal of bottom transistor connected to ground) and a control terminal (Fig. 2A, gate terminal of bottom transistor), wherein the first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor) of the second switch (Fig. 2A, bottom transistor) is coupled to the second terminal (Fig. 2A, terminal of top transistor connected to inductor and bottom transistor) of the first switch (Fig. 2A, top transistor), and the second terminal (Fig. 2A, terminal of bottom transistor connected to ground) of the second switch (Fig. 2A, bottom transistor) is configured to be coupled to a reference voltage level (Fig. 2A, ground terminal).
Regarding claim 3, Lee et al further discloses an output pin (Fig. 3, output terminal) configured to provide a phase current for a multiphase voltage regulator (Fig. 3, circuit of 1st and 2nd power stages 12 and 22 respectively), wherein the output pin (Fig. 3, output terminal) is coupled to the first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor) of the second switch (Fig. 2A, bottom transistor) of the first power unit (Fig. 3, 1st phase power stage 12) and the first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor) of the second switch (Fig. 2A, bottom transistor) of the second power unit (Fig. 3, 2nd phase power stage 22).
Regarding claim 4, Lee et al further comprising a first output pin (Fig. 3, output terminal from 1st phase power stage 12) coupled to the first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor) of the second switch (Fig. 2A, bottom transistor) of the first power unit (Fig. 3, 1st phase power stage 12), wherein the first output pin (Fig. 3, output terminal from 1st phase power stage 12) is configured to provide the first current (Fig. 3, current I1 outputted from power stage 12); and
a second output pin (Fig. 3, output terminal from 2nd phase power stage 22) coupled to the first terminal (Fig. 2A, terminal of bottom transistor connected to inductor and bottom transistor) of the second switch (Fig. 2A, bottom transistor) of the second power unit (Fig. 3, 2nd phase power stage 22), wherein the second output pin (Fig. 3, output terminal from 2nd phase power stage 22) is configured to provide the second current (Fig. 3, current I2 outputted from power stage 22);
wherein the sum of the first current (Fig. 3, current I1 outputted from power stage 12) and the second current (Fig. 3, current I2 outputted from power stage 22) is a phase current for a multiphase voltage regulator (Fig. 3, circuit of 1st and 2nd power stages 12 and 22 respectively).
Regarding claim 5, Lee et al further discloses wherein the control signal (Fig. 3, phase OFF signal) indicates a power mode (i.e. mode determining how many of the one or more of the at least one second phase power stages are active. See ¶[0011]).
Regarding claim 6, Lee et al further discloses wherein the control signal (Fig. 3, phase OFF signal) indicates a load signal (i.e. phase OFF signal can distribute current loading among active power stages. See ¶[0011]).
Regarding claim 18, Lee et al discloses a multiphase voltage regulator (Fig. 3, circuit of 1st and 2nd power stages 12 and 22 respectively), comprising:
a plurality of power stage circuits (Fig. 3, 1st phase power stage 12 and 2nd phase power stage 22), each of which is configured to provide a phase current (Fig. 3, current I1 outputted from power stage 12 and current I2 outputted from power stage 22) (See ¶[0004]); and
a control circuit (Fig. 3, circuit of current balance circuit 14, 1st phase pwm controller 11, 2nd phase pwm controller 21, and soft shutdown control circuit 15) coupled to the power stage circuits (Fig. 3, 1st phase power stage 12 and 2nd phase power stage 22);
wherein a first power stage circuit (Fig. 3, 1st phase power stage 12) has a first current capability (Fig. 3, current I1 outputted from power stage 12) (See ¶[0004]); and the other power stage circuits (Fig. 3, 2nd phase power stage 22) have a second current capability (Fig. 3, current I2 outputted from power stage 22) (See ¶[0004]) greater than the first current capability (Fig. 3, current I1 outputted from power stage 12) (i.e. either current I1 or I2 can be higher than the other since current balance circuit 14 receives signals indicative of the current signals, and generates to current balance signal so that current I1 and I2 are balanced. (See ¶[0004]);
wherein the power stage circuit (Fig. 3, circuit of 1st phase power stage 12 and 2nd phase power stage 22) comprises:
a switching control pin (Fig. 3, terminal of 2nd PWM controller 21 receiving soft shutdown signal) configured to receive a control signal (Fig. 3, soft shutdown signal) from the control circuit (Fig. 3, circuit of current balance circuit 14, 1st phase pwm controller 11, 2nd phase pwm controller 21, and soft shutdown control circuit 15);
a power unit (Fig. 2A, top transistor) comprises at least one power switch (Fig. 2A, top transistor) and is configured to provide the phase current (Fig. 3, current I1 outputted from power stage 12 and current I2 outputted from power stage 22); and
a driving control circuit (Fig. 3, circuit of 1st phase PWM controller 11 and 2nd phase PWM controller 21) configured to provide a driving signal (Fig. 3, signals PWM1 or PWM2) to the power unit (Fig. 2A, top transistor) in response to the control signal (Fig. 3, soft shutdown signal);
wherein the first power stage circuit (Fig. 3, 1st phase power stage 12) is configured to provide a first current (Fig. 3, current I1 outputted from power stage 12) to a load (Fig. 3, load circuit capable of coupling to signal Vout); and each of the other power stage circuits (Fig. 3, 2nd phase power stage 22) is configured to provide a second current (Fig. 3, current I2 outputted from power stage 22) greater than the first current (Fig. 3, current I1 outputted from power stage 12) to the load (Fig. 3, load circuit capable of coupling to signal Vout) (i.e. either current I1 or I2 can be higher than the other since current balance circuit 14 receives signals indicative of the current signals, and generates to current balance signal so that current I1 and I2 are balanced. (See ¶[0004]).
Allowable Subject Matter
6. Claims 13-17 are allowed.
7. Claims 7-12 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit, further comprising:
a mode pin coupled to the driving control circuit, wherein the mode pin is configured to receive a mode signal;
wherein the first power unit is turned on and the second power unit is turned off when the mode signal is at a first logic level.
Regarding claim 8, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit, further comprising:
a mode pin coupled to the driving control circuit, wherein the mode pin is configured to receive a mode signal;
wherein the first power unit and the second power unit are turned on to perform a switching operation when the mode signal is at a second logic level.
Regarding claim 9, the prior art fails to disclose or suggest the emboldened and italicized features below:
The integrated circuit of claim 1, further comprising:
a mode pin coupled to the driving control circuit, wherein the mode pin is configured to receive a mode signal;
wherein the first power unit is turned off and the second power unit is turned on to perform a switching operation when the mode signal is at a second logic level.
Regarding claim 10, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit, further comprising:
a mode pin coupled to the driving control circuit, wherein the mode pin is configured to receive a mode signal;
wherein the first power unit and the second power unit are turned off when the mode signal is at a third logic level.
Regarding claim 11, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit,
wherein the driving control circuit is further configured to determine whether the first current sense signal is greater than a first threshold; and the second power unit is turned on when the first current sense signal is greater than the first threshold.
Regarding claim 12, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit,
wherein the driving control circuit is further configured to determine whether a sum of the first current sense signal and the second current sense signal is less than a second threshold; and the second power unit is turned off when the sum of the first current sense signal and the second current sense signal is less than the second threshold.
Regarding claims 13-17, the prior art fails to disclose or suggest the emboldened and italicized features below:
An integrated circuit, comprising:
a switching control pin configured to receive a control signal;
a first power unit having a first current capability;
a second power unit having a second current capability, wherein the second current capability is greater than the first current capability;
a driving control circuit configured to provide a first driving signal to the first power unit in response to the control signal, and to provide a second driving signal to the second power unit in response to the control signal, wherein the first power unit and the second power unit are configured to provide a phase current for a multiphase voltage regulator; and
a current sense circuit configured to provide a current sense signal indicating the phase current;
wherein the driving control circuit is further configured to determine whether the current sense signal is within the first current capability; and
wherein the first power unit is turned on and the second power unit is turned off when the current sense signal is within the first current capability.
Regarding claim 19, the prior art fails to disclose or suggest the emboldened and italicized features below:
A multiphase voltage regulator,
wherein the second current is proportional to the first current under different load currents.
Regarding claim 20, the prior art fails to disclose or suggest the emboldened and italicized features below:
A multiphase voltage regulator,
wherein the control circuit is further configured to determine whether a phase current is within the first current capability; wherein when the phase current exceeds the first current capability, the control circuit is configured to limit the first current within the first current capability and perform a current sharing calculation to determine the second current.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yao et al (US 2023/0123031) deals with a multi-phase power converter, control circuit and control method thereof, Upadhyaya (US 2022/0263401) deals with a phase redundant power supply with oring fet current sensing, Schmitz (US 2020/0295658) deals with a switching regulator controller configuration parameter optimization, Nora (US 2014/0375288) deals with a current sharing method for a cot buck converter, Chen et al (US 8,836,298) deals with a multi-phase switching regulator and control method thereof, and Chang et al (US 2012/0176105) deals with a multi-phase switching regulator and driver circuit and control method thereof.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY A NASH/Primary Examiner, Art Unit 2838
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