DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 202310791870.4, filed on 08th, Aug. 2023.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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3. Claim(s) 1-7, 9-10, 13-14, and 16-20 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim(s) 1-4, 6-9, 12, and 17 of U.S. Patent No. 12,230,194. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application’s claims are essentially broader than the patent’s recited claims.
Instant Application 19/036908
U.S. Patent No. 12,230,194
1. A display panel, comprising a substrate and a drive circuit located on one side of the substrate;
wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor;
the drive circuit further comprises a first capacitor and a shift register circuit, and one capacitor plate of the first capacitor is disposed in a same layer as the first active layer;
the shift register circuit comprises a bootstrap capacitor and an output transistor, one terminal of the bootstrap capacitor is electrically connected to an output terminal of the shift register circuit, and the other terminal of the bootstrap capacitor is electrically connected to a gate of the output transistor;
the first capacitor comprises the bootstrap capacitor, and one capacitor plate of the bootstrap capacitor is disposed in a same layer as the first active layer.
1. A display panel, comprising a substrate and a drive circuit located on one side of the substrate;
wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor; and
the drive circuit further comprises a first capacitor, and one capacitor plate of the first capacitor is disposed in a same layer as the first active layer…
3. The display panel of claim 1, wherein the drive circuit further comprises a shift register circuit,
the shift register circuit comprises a bootstrap capacitor and an output transistor, one terminal of the bootstrap capacitor is electrically connected to an output terminal of the shift register circuit, and another terminal of the bootstrap capacitor is electrically connected to a gate of the output transistor; …; and
the first capacitor further comprises the bootstrap capacitor, one capacitor plate of the bootstrap capacitor is disposed in a same layer as the first active layer, ….
2. The display panel of claim 1, wherein the first transistor further comprises a first gate located on a side of the first active layer away from the substrate; and
the other capacitor plate of the bootstrap capacitor is disposed in a same layer as the first gate.
2. The display panel of claim 1, wherein … the first transistor further comprises a first gate located on a side of the first active layer away from the substrate, and one capacitor plate of the node potential adjustment capacitor is disposed in a same layer as the first gate.
3. The display panel of claim 1, wherein the drive circuit further comprises second transistors, one of the second transistors comprises a second active layer, and the second active layer comprises silicon; and the display panel further comprises a second connection structure, a source and a drain of at least a portion of the second transistors are electrically connected to the second active layer via the second connection structure, and the second connection structure is disposed in the same layer as the first active layer.
7. The display panel of claim 1, wherein the drive circuit further comprises second transistors, one of the second transistors comprises a second active layer, and the second active layer comprises silicon; and the display panel further comprises a second connection structure, a source and a drain of at least a portion of the second transistors are electrically connected to the second active layer via the second connection structure, and the second connection structure is disposed in a same layer as the first active layer.
4. The display panel of claim 3, wherein the drive circuit further comprises a pixel circuit, and
the second transistors comprise a switch transistor and a drive transistor; at least a source and a drain of the switch transistor are electrically connected to the second active layer via the second connection structure.
1. A display panel, … wherein the drive circuit comprises a pixel circuit,
8. The display panel of claim 7, wherein
the second transistor comprises a switch transistor and a drive transistor; and at least a source and a drain of the switch transistor are electrically connected to the second active layer via the second connection structure.
5. The display panel of claim 3, wherein the source and the drain of a second transistor in the shift register circuit are electrically connected to the second active layer via the second connection structure.
9. The display panel of claim 7, wherein … the source and the drain of the second transistor in the shift register circuit are electrically connected to the second active layer via the second connection structure.
6. The display panel of claim 1, wherein the drive circuit further comprises a pixel circuit, the pixel circuit comprises a storage capacitor, and one capacitor plate of the storage capacitor is electrically connected to a power signal terminal; and
the first capacitor further comprises the storage capacitor.
2. The display panel of claim 1, wherein
the pixel circuit further comprises a storage capacitor, one capacitor plate of the storage capacitor is electrically connected to a power signal terminal;
the first capacitor further comprises the storage capacitor; ...
7. The display panel of claim 1, wherein the drive circuit further comprises a pixel circuit, the pixel circuit comprises a data writing transistor, a drive transistor, and a node potential adjustment capacitor, wherein the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor; and the first capacitor further comprises the node potential adjustment capacitor.
1. A display panel, …wherein
the drive circuit comprises a pixel circuit, the pixel circuit comprises a data writing transistor, a drive transistor, and a node potential adjustment capacitor,
wherein the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor; and the first capacitor comprises the node potential adjustment capacitor.
9. The display panel of claim 1, wherein the drive circuit further comprises a pixel circuit, and
the pixel circuit comprises a light-emitting control transistor, an initialization transistor, and a bias adjustment transistor;
the display panel further comprises a light-emitting control signal line, an initialization signal line, and a bias adjustment signal line, wherein the light-emitting control signal line is electrically connected to a gate of the light-emitting control transistor, the initialization signal line is electrically connected to an input terminal of the initialization transistor, and the bias adjustment signal line is electrically connected to an input terminal of the bias adjustment transistor; and
at least one of the light-emitting control signal line, the initialization signal line, or the bias adjustment signal line is disposed in the same layer as the first active layer.
4. The display panel of claim 1, wherein
the pixel circuit further comprises a light-emitting control transistor, an initialization transistor, and a bias adjustment transistor;
the display panel further comprises a light-emitting control signal line, an initialization signal line, and a bias adjustment signal line, wherein the light-emitting control signal line is electrically connected to a gate of the light-emitting control transistor, the initialization signal line is electrically connected to an input terminal of the initialization transistor, and the bias adjustment signal line is electrically connected to an input terminal of the bias adjustment transistor; and
at least one of the light-emitting control signal line, the initialization signal line, or the bias adjustment signal line is disposed in a same layer as the first active layer.
10. The display panel of claim 1, wherein the drive circuit further comprises a pixel circuit, the pixel circuit comprises a drive transistor and a threshold compensation transistor, and an output terminal of the threshold compensation transistor is electrically connected to a gate of the drive transistor via a first connection structure; and
the first connection structure is disposed in the same layer as the first active layer.
1. A display panel, comprising … a drive transistor…
6. The display panel of claim 1, wherein the pixel circuit further comprises a threshold compensation transistor, and an output terminal of the threshold compensation transistor is electrically connected to the gate of the drive transistor via a first connection structure; and
the first connection structure is disposed in a same layer as the first active layer.
13. The display panel of claim 1, wherein the display panel comprises a first display region and a second display region, and the second display region at least partially surrounds the first display region;
wherein the first display region comprises a first light-emitting element, and the second display region comprises a second light-emitting element;
the drive circuit comprises a first pixel circuit and a second pixel circuit which are located in the second display region, the first pixel circuit is electrically connected to the first light-emitting element via a third connection structure, and the second pixel circuit is electrically connected to the second light-emitting element; and
the third connection structure is disposed in the same layer as the first active layer.
12. The display panel of claim 1, wherein the display panel comprises a first display region and a second display region, and the second display region at least partially surrounds the first display region;
wherein the first display region comprises a first light-emitting element, and the second display region comprises a second light-emitting element;
the pixel circuit comprises a first pixel circuit and a second pixel circuit which are located in the second display region, the first pixel circuit is electrically connected to the first light-emitting element via a third connection structure, and the second pixel circuit is electrically connected to the second light-emitting element; and
the third connection structure is disposed in a same layer as the first active layer.
14. A display device, comprising the display panel according to claim 1.
17. A display device, comprising a display panel,
16. A display panel, comprising a substrate and a drive circuit located on one side of the substrate; wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor; and
the drive circuit further comprises a pixel circuit, and the pixel circuit comprises a light-emitting control transistor, an initialization transistor, and a bias adjustment transistor;
the display panel further comprises a light-emitting control signal line, an initialization signal line, and a bias adjustment signal line, wherein the light-emitting control signal line is electrically connected to a gate of the light-emitting control transistor, the initialization signal line is electrically connected to an input terminal of the initialization transistor, and the bias adjustment signal line is electrically connected to an input terminal of the bias adjustment transistor; and
at least one of the light-emitting control signal line, the initialization signal line, or the bias adjustment signal line is disposed in a same layer as the first active layer.
1. A display panel, comprising a substrate and a drive circuit located on one side of the substrate; wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor; and
4. The display panel of claim 1, wherein the pixel circuit further comprises a light-emitting control transistor, an initialization transistor, and a bias adjustment transistor;
the display panel further comprises a light-emitting control signal line, an initialization signal line, and a bias adjustment signal line, wherein the light-emitting control signal line is electrically connected to a gate of the light-emitting control transistor, the initialization signal line is electrically connected to an input terminal of the initialization transistor, and the bias adjustment signal line is electrically connected to an input terminal of the bias adjustment transistor; and
at least one of the light-emitting control signal line, the initialization signal line, or the bias adjustment signal line is disposed in a same layer as the first active layer.
17. The display panel of claim 16, wherein the drive circuit further comprises a first capacitor, and one capacitor plate of the first capacitor is disposed in the same layer as the first active layer.
1. A display panel, …
the drive circuit further comprises a first capacitor, and one capacitor plate of the first capacitor is disposed in a same layer as the first active layer;
18. The display panel of claim 17, wherein the pixel circuit further comprises a data writing transistor, a drive transistor, and a node potential adjustment capacitor, wherein the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor; and
the first capacitor comprises the node potential adjustment capacitor.
1. A display panel, comprising …
the pixel circuit comprises
a data writing transistor, a drive transistor, and a node potential adjustment capacitor, wherein the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor; and
the first capacitor comprises the node potential adjustment capacitor.
19. The display panel of claim 17, wherein the pixel circuit further comprises a data writing transistor, a drive transistor, a storage capacitor, and a node potential adjustment capacitor, one capacitor plate of the storage capacitor is electrically connected to a power signal terminal, and
the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor;
the first capacitor comprises the storage capacitor; and
the first transistor further comprises a first gate located on a side of the first active layer away from the substrate, and one capacitor plate of the node potential adjustment capacitor is disposed in a same layer as the first gate.
1. A display panel, comprising …
the pixel circuit comprises a data writing transistor, a drive transistor, and a node potential adjustment capacitor, wherein
1. A display panel, …
the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor; and
2. The display panel of claim 1, wherein… the first capacitor further comprises the storage capacitor; and
the first transistor further comprises a first gate located on a side of the first active layer away from the substrate, and one capacitor plate of the node potential adjustment capacitor is disposed in a same layer as the first gate.
20. A display device, comprising the display panel according to claim 16.
17. A display device, comprising a display panel…
4. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 12,230,194 in view of Zhang et al. (U.S. Patent No. 12408549).
15. A display panel, comprising a substrate and a drive circuit located on one side of the substrate; wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor; and
the display panel further comprises a fan-out wire region and a fan-out wire located in the fan-out wire region;
the fan-out wire is connected to a data line and a drive chip; and
the fan-out wire comprises at least one layer of wire structures, and at least a portion of the fan-out wire is disposed in a same layer as the first active layer.
1. A display panel, comprising a substrate and a drive circuit located on one side of the substrate; wherein the drive circuit comprises a first transistor, the first transistor comprises a first active layer, and the first active layer comprises an oxide semiconductor; and
5. The display panel of claim 1, wherein the display panel further comprises a fan-out wire region and a fan-out wire located in the fan-out wire region; and
the fan-out wire comprises at least one layer of wire structures, and at least a portion of the fan-out wire is disposed in a same layer as the first active layer.
U.S. Patent No. 12,230,194 recites the display panel of Claim 15.
However, U.S. Patent No. 12,230,194 does not recite
the fan-out wire is connected to a data line and a drive chip.
In the same field of endeavor, Zhang et al. teach
the fan-out wire (Col. 3, Ln. 42-48, FIG. 1, i.e. fan-out region) is connected to (Col. 3, Ln. 42-48, FIG. 1, i.e. electrically connected) a data line (Col. 3, Ln. 42-48, FIG. 1, i.e. third data signal lines) and a drive chip (Col. 3, Ln. 42-48, FIG. 1, i.e. driving chip).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine U.S. Patent No. 12,230,194 teaching of display panel comprising electronics and fan-out region with Zhang et al. teaching of display panel connecting chip and data line in fan-out region to effectively provide data signals to data signal lines in a display region from a densely arranged horizontal direction (Zhang et al.’s (Col. 5, Ln. 12-17)).
Allowable Subject Matter
5. Claim(s) 8 and 11-12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for allowance:
LI et al. (US PGPUB./Pat. No. 12230194) teach a display panel and a display device. The display panel includes a substrate and a drive circuit disposed on one side of the substrate. The drive circuit includes a first transistor. The first transistor includes a first active layer. The first active layer includes an oxide semiconductor. The drive circuit also includes a first capacitor. One capacitor plate of the first capacitor is disposed in the same layer as the first active layer. In the display panel according to embodiments of the present disclosure, a substrate of a first capacitor in a drive circuit is disposed in the same layer as an active layer of an oxide semiconductor.
Zhang et al. (U.S. Patent No. 12408549) teach a display substrate and a display apparatus are provided. The display substrate includes: a display region and a non-display region, the non-display region including a fan-out region and a bending region; a plurality of sub-pixels located in the display region; a plurality of first data signal lines located in the display region and electrically connected with the plurality of sub-pixels; a plurality of fan-out wires located in the fan-out region; a plurality of second data signal lines located in the bending region; and a plurality of transfer lines located in the fan-out region and between the plurality of fan-out wires and the plurality of second data signal lines, wherein a ratio of a width of at least part of the plurality of transfer lines to a width of the plurality of fan-out wires is 0.5 to 5.5.
The subject matter of the independent claims could either not be found or was not suggested in the prior art of record. The subject matter not found was a display device including
“…the drive circuit further comprises a pixel circuit, the pixel circuit comprises a data writing transistor, a drive transistor, a storage capacitor, and a node potential adjustment capacitor, one capacitor plate of the storage capacitor is electrically connected to a power signal terminal, and the node potential adjustment capacitor is disposed in series between a gate of the data writing transistor and a gate of the drive transistor;
the first capacitor further comprises the storage capacitor; and
the first transistor further comprises a first gate located on a side of the first active layer away from the substrate, and one capacitor plate of the node potential adjustment capacitor is disposed in a same layer as the first gate.” (Claim 8),
“…the drive circuit further comprises a second transistor, the second transistor comprises a second active layer, a source, and a drain, the second active layer comprises silicon, and the source and the drain are both electrically connected to the second active layer;
wherein the source comprises a first source portion and a second source portion, the first source portion is located on a side of the second source portion adjacent to the second active layer, the first source portion comprises a first source surface adjacent to one side of the second source portion, and the second source portion comprises a second source surface adjacent to one side of the first source portion;
the drain comprises a first drain portion and a second drain portion, the first drain portion is located on a side of the second drain portion adjacent to the second active layer, the first drain portion comprises a first drain surface adjacent to one side of the second drain portion, and the second drain portion comprises a second drain surface adjacent to one side of the first drain portion; and
the display panel further comprises at least one of a source connection portion or a drain connection portion, wherein the source connection portion is located between a film in which the first source portion is disposed and a film in which the second source portion is disposed, the source connection portion is electrically connected to the first source portion and the second source portion separately, and an area of the source connection portion is larger than both an area of the first source surface and an area of the second source surface;
the drain connection portion is located between a film in which the first drain portion is disposed and a film in which the second drain portion is disposed, the drain connection portion is electrically connected to the first drain portion and the second drain portion separately, and an area of the drain connection portion is larger than both an area of the first drain surface and an area of the second drain surface.” (Claim 11),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571) 270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
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/VINH T LAM/ Primary Examiner, Art Unit 2628