DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The Information Disclosure Statement filed on 24 January 2025 and 14 August 2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184).
Claim 1:
Ichida et al. disclose a memory chip comprising:
a memory cell array [figs. 1, 3, 4; par. 0076 – “As shown in FIG. 4, an explanation is given taking as an example, a NAND chip 2c from the NAND chips 1 to k. The NAND chip 2c includes a memory cell array 20, a row decoder 21, a column gate 22, address register 23, a data input/output buffer 24, a command I/F 25, and a state machine 26.”];
a temperature sensor configured to output first temperature data about a temperature of the memory chip [par. 0240 – “For example, as described in the sixth embodiment, by disposing a temperature sensor 9 for each NAND package 2 or each NAND chip 2c, temperature information for each NAND package 2 or NAND chip 2c can be stored in a temperature management section 51d.”];
an interface through which the second temperature data can be output to outside the memory chip [figs. 1, 3, 4, 39-40; pars. 0051, 0070, 0146, 0240 – “a temperature storage configured to store temperature information received from the temperature measurement section, and a temperature controller configured to control the temperature varying section based on the temperature information stored in the temperature storage.” … “The temperature management section 51d manages temperature information and so on about the NAND memories 2 measured by a temperature sensor (described below). This temperature information and so on can be rewritten if needed. When managing temperature information and so on about the NAND memories 2 or NAND chips, a dedicated table, for exempla, may be prepared, and the temperature information and so on may be stored so as to be correlated with the identification numbers of NAND memories 2 or NAND chips.” … “Then, the temperature sensor 9 supplies the measurement result (temperature information) to a temperature management section 51d. This temperature information is stored in the temperature management section 51d. Alternatively, the temperature sensor 9 may measure the temperature of the SSD 1 or NAND memories 2 periodically (e.g., every predetermined clock interval) and supply the measurement result to the temperature management section 51d.”].
However, Ichida et al. do not specifically disclose,
a stress sensor configured to output first stress data about a stress applied to the memory chip;
a correction circuit configured to generate second temperature data about the temperature of the memory chip by correcting the first temperature data based on the first stress data; and
In the same field of endeavor, Haspeslagh et al. disclose,
a stress sensor configured to output first stress data about a stress applied to the memory chip [pars. 0015-0018 – “Each of the MEMS elements is also provided with at least one piezoresistor sensing element for generating an analogue sensor signal indicative of displacement of the MEMS element, and a temperature sensor for generating an analogue temperature signal indicative of the temperature of the piezoresistor sensing element.”];
a correction circuit configured to generate second temperature data about the temperature of the memory chip by correcting the first temperature data based on the first stress data [pars. 0015-0018 – “The calculation may include modeling the strain in the temperature sensor. In this model, the temperature value indicated by the digital temperature signal is corrected to compensate for strain in the temperature sensor, which influences the output of the temperature sensor. The correction is performed using the digital sensor signal, and may include 1.sup.st, 2.sup.nd and/or 3.sup.rd order dependency on the digital sensor signal.”]; and
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ichida et al. to include correcting the temperature reading, as taught by Haspeslagh et al., in order to improve data integrity by providing a more accurate temperature reading for use in making decisions pertaining to management of the memory.
Claim 4 (as applied to claim 1 above):
Haspeslagh et al. disclose,
wherein the stress sensor includes a piezoresistor, and the stress sensor outputs the first stress data using the piezoresistor [pars. 0015-0018 – “Each of the MEMS elements is also provided with at least one piezoresistor sensing element for generating an analogue sensor signal indicative of displacement of the MEMS element,”].
Claim 9:
Ichida et al. disclose a memory system comprising:
the memory chip according to claim 1 [see claim 1]; and
a memory controller including a processor configured to control writing of data to the memory cell array, reading of data from the memory cell array, or erasing of data from the memory cell array, based on the second temperature data, wherein the second temperature data is received from the memory chip through the interface [figs. 1-3, 4, 39-40; pars. 0061-70, – drive control circuit 5].
Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) as applied to claims 1 and 9 above, respectively, and further in view of Formenti et al. (Pub. No. US 2022/0187378).
Claim 2 (as applied to claim 1 above):
Ichida et al. and Haspeslagh et al. disclose all the limitations above but do not specifically disclose the memory chip, further comprising:
a stress correction table including information for correcting the first temperature data to the second temperature data based on the first stress data, wherein the correction circuit generates the second temperature data using the first stress data and the stress correction table.
In the same field of endeavor, Formenti et al. disclose,
a stress correction table including information for correcting the first temperature data to the second temperature data based on the first stress data, wherein the correction circuit generates the second temperature data using the first stress data and the stress correction table [par. 0032 – “In respective battery monitoring cycles 140, the digital circuit 130 stores the converted values internally, and uses these values along with the correction parameters 131-133 and associated equations or formulas (e.g., parametric and/or lookup tables) to digitally correct the initial converted battery voltage value or values from the ADC 110 and to compute and store corresponding corrected battery voltage values based on digital stress sensor X/Y outputs and the converted temperature value Tj.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al. and Haspeslagh et al. to include a table, as taught by Formenti et al., in order to improve performance by providing a simple means for performing the value correction.
Claim 10 (as applied to claim 9 above):
Claim 10, directed to a memory system, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) and Formenti et al. (Pub. No. US 2022/0187378) as applied to claims 2 and 10 above, respectively, and further in view of Park et al. (Pub. No. US 2008/0094914).
Claim 3 (as applied to claim 2 above):
Ichida et al., Haspeslagh et al., and Formenti et al. disclose all the limitations above but do not specifically disclose the memory chip, further comprising:
a register in which the stress correction table, the first temperature data, and the first stress data are stored.
In the same field of endeavor, Park et al. disclose,
a register in which the stress correction table, the first temperature data, and the first stress data are stored [par. 0053 – “The memory controller 2000 according to embodiments of the present invention may further include a register 2100 for storing a table of wear-leveling values and a data recover/restore controller 2200. The register 2100 may be used to store a table of wear-leveling values of memory blocks that are provided from the wear-leveling table region of the flash memory device 1000.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al., Haspeslagh et al., and Formenti et al. to include storing data in a register, as taught by Park et al., in order to improve performance by using a high speed memory.
Claim 11 (as applied to claim 10 above):
Claim 11, directed to a memory system, is rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Claim(s) 5, 6, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) as applied to claim 1 and 9 above, respectively, and further in view of Chen et al. (Pub. No. US 2009/0091996).
Claim 5 (as applied to claim 1 above):
Ichida et al. and Haspeslagh et al. disclose all the limitations above but do not specifically disclose,
wherein the memory chip is configured to operate in a first mode or in a second mode, based on control from outside the memory chip.
In the same field of endeavor, Chen et al. disclose,
wherein the memory chip is configured to operate in a first mode or in a second mode, based on control from outside the memory chip [figs. 4-5; pars. 0029-0035 – “Therefore, the solid state semiconductor storage device with temperature control function alters the operation speed of the control unit 43 and the accessing speed to the non-volatile memory unit 42 according to the temperature sensing results, so that the heat can be effectively dispersed and thus the stable operation can be achieved.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al. and Haspeslagh et al. to include adjusting the operating speed according to the temperature, as taught by Chen et al., in order to increase stability and extend the lifetime of the storage device.
Claim 6 (as applied to claim 5 above):
Chen et al. disclose,
wherein in the first mode, the memory chip operates at a first processing speed, and in the second mode, the memory chip operates at a second processing speed that is slower than the first processing speed [figs. 4-5; pars. 0029-0035 – “When the temperature sensing signal outputted by the sensing element 44 of the solid state semiconductor storage device 4 is higher than the first temperature threshold T1, the storage device enters a second operation mode M2, namely a low-speed temperature dropping mode, as indicated by S1 shown in FIG. 5.”].
Claim 12 (as applied to claim 9 above):
Claim 12, directed to a memory system, is rejected for the same reasons set forth in the rejection of claim 5 above, mutatis mutandis.
Claim 13 (as applied to claim 12 above):
Claim 13, directed to a memory system, is rejected for the same reasons set forth in the rejection of claim 6 above, mutatis mutandis.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) as applied to claim 1 and 9 above, respectively, and further in view of Kutz et al. (Pub. No. US 2007/0217271).
Claim 7 (as applied to claim 1 above):
Ichida et al. and Haspeslagh et al. disclose all the limitations above but do not specifically disclose the memory chip, further comprising:
a voltage generation circuit configured to generate a voltage based on the second temperature data and apply the generated voltage to the memory cell array.
In the same field of endeavor, Kutz et al. disclose,
a voltage generation circuit configured to generate a voltage based on the second temperature data and apply the generated voltage to the memory cell array [par. 0035 – “In one embodiment, register 430 stores a plurality of program values each indicating a different program voltage VP to be applied at a given operating temperature range. Alternatively, register 430 may store temperature scaling factors to be applied to the single program value based on the current operating temperature. Register 430 may also store a plurality of program values or aging scaling factors that may be used to adjust the program voltage VP based on the age of NV memory array 305. Similarly, multiple erase values or temperature/aging scaling factors may be stored to adjust the erase voltage VE based on operating temperature and/or age. Similarly, multiple read values or temperature/aging scaling factors may be stored to adjust the read voltage VR based on operating temperature and/or age.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al. and Haspeslagh et al. to include adjusting voltages according to operating temperatures, as taught by Kutz et al., in order to increase data integrity.
Claim 14 (as applied to claim 9 above):
Claim 14, directed to a memory system, is rejected for the same reasons set forth in the rejection of claim 7 above, mutatis mutandis.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) and Chen et al. (Pub. No. US 2009/0091996).
Claim 16:
Ichida et al. disclose a memory system comprising:
a memory chip including [figs. 1, 3, 4; par. 0076 – “As shown in FIG. 4, an explanation is given taking as an example, a NAND chip 2c from the NAND chips 1 to k. The NAND chip 2c includes a memory cell array 20, a row decoder 21, a column gate 22, address register 23, a data input/output buffer 24, a command I/F 25, and a state machine 26.”] a memory cell array and a temperature sensor configured to output first temperature data about a temperature of the memory chip [par. 0240 – “For example, as described in the sixth embodiment, by disposing a temperature sensor 9 for each NAND package 2 or each NAND chip 2c, temperature information for each NAND package 2 or NAND chip 2c can be stored in a temperature management section 51d.”]; and
a memory controller including a processor that is configured to:
receive the first temperature data from the memory chip [par. 0240 – “For example, as described in the sixth embodiment, by disposing a temperature sensor 9 for each NAND package 2 or each NAND chip 2c, temperature information for each NAND package 2 or NAND chip 2c can be stored in a temperature management section 51d.”]; and
However, Ichida et al. do not specifically disclose,
the memory chip including a stress sensor configured to output first stress data about a stress applied to the memory chip;
the memory controller to:
receiving first stress data from the memory chip;
generate second temperature data by correcting the first temperature data based on the first stress data;
In the same field of endeavor, Haspeslagh et al. disclose,
the memory chip including a stress sensor configured to output first stress data about a stress applied to the memory chip [pars. 0015-0018 – “Each of the MEMS elements is also provided with at least one piezoresistor sensing element for generating an analogue sensor signal indicative of displacement of the MEMS element, and a temperature sensor for generating an analogue temperature signal indicative of the temperature of the piezoresistor sensing element.”];
the memory controller to:
receiving first stress data from the memory chip [pars. 0015-0018 – “Each of the MEMS elements is also provided with at least one piezoresistor sensing element for generating an analogue sensor signal indicative of displacement of the MEMS element, and a temperature sensor for generating an analogue temperature signal indicative of the temperature of the piezoresistor sensing element.”];
generate second temperature data by correcting the first temperature data based on the first stress data [pars. 0015-0018 – “The calculation may include modeling the strain in the temperature sensor. In this model, the temperature value indicated by the digital temperature signal is corrected to compensate for strain in the temperature sensor, which influences the output of the temperature sensor. The correction is performed using the digital sensor signal, and may include 1.sup.st, 2.sup.nd and/or 3.sup.rd order dependency on the digital sensor signal.”];
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ichida et al. to include correcting the temperature reading, as taught by Haspeslagh et al., in order to improve data integrity by providing a more accurate temperature reading for use in making decisions pertaining to management of the memory.
Ichida et al. and Haspeslagh et al. disclose all the limitations above but do not specifically disclose,
the memory controller to:
control writing of data to the memory cell array, reading of data from the memory cell array, or erasing of data from the memory cell array, based on the second temperature data.
In the same field of endeavor, Chen et al. disclose,
the memory controller to:
control writing of data to the memory cell array, reading of data from the memory cell array, or erasing of data from the memory cell array, based on the second temperature data [figs. 4-5; pars. 0029-0035 – “Therefore, the solid state semiconductor storage device with temperature control function alters the operation speed of the control unit 43 and the accessing speed to the non-volatile memory unit 42 according to the temperature sensing results, so that the heat can be effectively dispersed and thus the stable operation can be achieved.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al. and Haspeslagh et al. to include adjusting the operating speed according to the temperature, as taught by Chen et al., in order to increase stability and extend the lifetime of the storage device.
Claim 17 (as applied to claim 16 above):
Haspeslagh et al. disclose,
wherein the stress sensor includes a piezoresistor, and the stress sensor outputs the first stress data using the piezoresistor [pars. 0015-0018 – “Each of the MEMS elements is also provided with at least one piezoresistor sensing element for generating an analogue sensor signal indicative of displacement of the MEMS element,”].
Claim 18 (as applied to claim 16 above):
Chen et al. disclose,
wherein the processor of the memory controller is further configured to control the memory system in a first mode or in a second mode, based on the second temperature data [figs. 4-5; pars. 0029-0035 – “Therefore, the solid state semiconductor storage device with temperature control function alters the operation speed of the control unit 43 and the accessing speed to the non-volatile memory unit 42 according to the temperature sensing results, so that the heat can be effectively dispersed and thus the stable operation can be achieved.”].
Claim 19 (as applied to claim 18 above):
Chen et al. disclose,
wherein in the first mode, the processor of the memory controller controls the memory system to operate at a first processing speed, and in the second mode, the processor of the memory controller controls the memory system to operate at a second processing speed that is lower than the first processing speed [figs. 4-5; pars. 0029-0035 – “When the temperature sensing signal outputted by the sensing element 44 of the solid state semiconductor storage device 4 is higher than the first temperature threshold T1, the storage device enters a second operation mode M2, namely a low-speed temperature dropping mode, as indicated by S1 shown in FIG. 5.”].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichida et al. (Pub. No. US 2013/0227268) in view of Haspeslagh et al. (Pub. No. US 2024/0004184) and Chen et al. (Pub. No. US 2009/0091996) as applied to claim 16 above, and further in view of Inada et al. (Pub. No. US 2012/0215965).
Claim 20 (as applied to claim 16 above):
Ichida et al., Haspeslagh et al., and Chen et al. disclose all the limitations above but do not specifically disclose the memory system, further comprising:
a volatile memory in which a stress correction table, the first temperature data, and the first stress data are stored.
In the same field of endeavor, Inada et al. disclose,
a volatile memory in which a stress correction table, the first temperature data, and the first stress data are stored [fig. 1; par. 0015 – RAM 23 for storing management information].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Ichida et al., Haspeslagh et al., and Chen et al. to include a RAM for storage management information, as taught by Inada et al., in order to improve performance.
Allowable Subject Matter
Claims 8 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose the limitations of the listed claims in conjunction with the limitations of the base claim and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsumoto (Pub. No. US 2010/0270659) discloses, “In this way, the eight memory chips (the memory chips at the first to eight steps) included in the first memory chip group 112 are laminated stepwise with positions of short sides thereof shifted along the long side direction with pad array sides of the memory chips directed in the same direction (the direction of the short side 103A) and such that the electrode pads 110 of the memory chips 109 on the lower step sides are exposed.” [pars. 0048-0052]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
21 February 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139